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All Journal International Journal of Electrical and Computer Engineering International Journal of Reconfigurable and Embedded Systems (IJRES) Indonesian Journal of Electrical Engineering and Computer Science
Mohd Tafir Mustaffa
Universiti Sains Malaysia
Computer Science & IT Economics, Econometrics & Finance Electrical & Electronics Engineering

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A Tunable Ferrofluid-based Polydimethylsiloxane (PDMS) Microchannel Inductor for Ultra High Frequency Applications Ahmad Hafiz Mohamad Razy; Mohd Tafir Mustaffa; Asrulnizam Abd Manaf; Norlaili Mohd Noh
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 2: April 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (683.176 KB) | DOI: 10.11591/ijece.v7i2.pp926-932

Abstract

In this work, a tunable ferrofluid-based polydimethylsiloxane (PDMS) microchannel inductor with high quality factor and high tuning range is proposed. For this project, PDMS is used to create a microchannel with a width and height of 0.53 mm and 0.2 mm respectively. The microchannel is then used to cover the whole design of a solenoid inductor. A solenoid inductor is designed using wire bonding technique where lines of copper and bond wires are used to form a solenoid winding on top of silicon substrate. A light hydrocarbon based ferrofluid EMG 901 660 mT with high permeability of 5.4 is used. The ferrofluid-based liquid is injected into the channel to enhance the performance of a quality factor. A 3D full-wave electromagnetic fields tool, ANSYS HFSS is used in this work to simulate the solenoid inductor. The results obtained in this work gives a quality factor of more than 10 at a frequency range of 300 MHz to 3.3 GHz (Ultra High Frequency range). The highest quality factor is 37 which occurs at a frequency of 1.5 GHz, provides a high tuning range of 112%.
A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques Mohd Tafir Mustaffa
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i3.pp221-229

Abstract

Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power.
Current Steering Digital Analog Converter with Partial Binary Tree Network (PBTN) Mohd Tafir Mustaffa; Yong Cheng Lim; Choon Yan Teh
Indonesian Journal of Electrical Engineering and Computer Science Vol 5, No 3: March 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v5.i3.pp643-649

Abstract

DACs are essential devices in many digital systems which require high performance data converters. Thus, shrinking of supply voltage, budget constraints of test times, and rising bandwidth requirement causing DAC architectures to highly relying on matched components to perform data conversions. However, matched components are nearly impossible to fabricate; there are always mismatch errors which causes the difference between the designed and actual component value. Dynamic Element Matching (DEM) is one of the techniques that are commonly used to reduce component mismatch error. This technique is a randomization technique to select one of the appropriate codes for each of the digital input value before entering DAC block. Thus, in this research, a new DEM algorithm is proposed on Current-Steering DAC with Partial Binary Tree Network (PBTN) algorithm that utilizes a lower complexity circuit to produce output signals with less glitches. Simulation results for 6-bit 1-MSB PBTN DAC produces 0.3184LSB of DNL, 0.0062LSB of INL, and a power consumption of 14.13 mW, while using only 126 transmission gates.
Development of Accurate BSIM4 Noise Parameters for CMOS 0.13-µm Transistors in Below 3-GHz LNA Application Asmaa Nur Aqilah Zainal Badri; Norlaili Mohd Noh; Shukri bin Korakkottil Kunhi Mohd; Asrulnizam Abd Manaf; Arjuna Marzuki; Mohd Tafir Mustaffa; Mohamed Fauzi Packeer Mohamed
Indonesian Journal of Electrical Engineering and Computer Science Vol 10, No 3: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v10.i3.pp925-933

Abstract

Accurate transistor thermal noise model is crucial in IC design as it allows accurate selection of transistors for specific frequency application. The accuracy of the model is represented by the similarity between the simulated and the measured noise parameters (NPs). This work was based on a problem faced by a foundry concerning the dissimilarities between the measured and simulated NPs, especially minimum noise figure (NFmin) for frequencies below 3 GHz.
Evaluation of PCB Shielding Characteristic in Near Field Yih Jian Chuah; Mohd Tafir Mustaffa
Indonesian Journal of Electrical Engineering and Computer Science Vol 5, No 3: March 2017
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v5.i3.pp542-548

Abstract

Wireless electronic devices nowadays always operate in high frequency while having small and compact form factor which led to electromagnetic interference among traces and components. PCB shielding is the common solution applied in electronic industry to mitigate electromagnetic interference. In this paper, PCB shielding characteristics such as shield’s thickness, height, and ground via spacing in PCB boards were evaluated in near field. Test boards with various ground via spacing were fabricated and evaluated by using 3D Electromagnetic scanner. On the other hand, shields with various thickness and height were modeled and evaluated through simulation. Results suggested that shielding effectiveness could be improved by having greater shield’s height with smaller ground via spacing in shielding ground tracks. Shielding effectiveness can be improved by 1 dB with every step of 0.5 mm increase in shield’s height. Besides that, approximately 0.5 dB improvement in shielding effectiveness with every step of 1 mm decrease in ground via spacing. Furthermore, greater shield’s thickness can contribute better shielding effectiveness for operating frequency below 300 MHz.
Co-Authors Ahmad Hafiz Mohamad Razy Arjuna Marzuki Asmaa Nur Aqilah Zainal Badri Asrulnizam Abd Manaf Choon Yan Teh Mohamed Fauzi Packeer Mohamed Norlaili Mohd Noh Shukri bin Korakkottil Kunhi Mohd Yih Jian Chuah Yong Cheng Lim