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All Journal International Journal of Electrical and Computer Engineering IAES International Journal of Artificial Intelligence (IJ-AI)
Srikantaswamy, Mallikarjunaswamy
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Computer Science & IT Electrical & Electronics Engineering Engineering

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Journal : international journal of electrical and computer engineering

 1 
An efficient adaptive reconfigurable routing protocol for optimized data packet distribution in network on chips Goravi Sukumar, Pavithra; Krishnaiah, Modugu; Velluri, Rekha; Satish, Pooja; Nagaraju, Sharmila; Gowda Puttaswamy, Nandini; Srikantaswamy, Mallikarjunaswamy
International Journal of Electrical and Computer Engineering (IJECE) Vol 14, No 1: February 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v14i1.pp305-314

Abstract

The deadlock-free and live lock-free routing at the same time is minimized in the network on chip (NoC) using the proposed adoptive reconfigurable routing protocol (ARRP). Congestion condition emergencies are avoided using the proposed algorithm. The input packet distribution process is improved among all its shortest paths of output points. The performance analysis has been initiated by considering different configuration (N*N) mesh networks, by sending various ranges of data packets to the network on chip. The average and maximum power dissipation of XY, odd-even, Dy-XY algorithm, and proposed algorithm are determined. In this paper, an analysis of gate utilization during data packet transfer in various mesh configurations is carried out. The number of cycles required for each message injection in different mesh configurations is analyzed. The proposed routing algorithm is implemented and compared with conventional algorithms. The simulation has been carried out using reconfigurable two-dimensional mesh for the NoC. The proposed algorithm has been implemented considering array size, the routing operating frequency, link width length, value of probability, and traffic types. The proposed ARRP algorithm reduces the average latency, avoids routing congestion, and is more feasible for NoC compared to conventional methods.
An efficient reconfigurable optimal source detection and beam allocation algorithm for signal subspace factorization Thazeen, Sadiya; Srikantaswamy, Mallikarjunaswamy
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 6: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i6.pp6452-6465

Abstract

Now a days, huge amount of data is communicated through channels in wireless network. It requires an efficient parallel operation for the optimal utilization of frequency, time allocation and coding model for signal subspace factorization in smart antenna. In view of this requirement, an efficient reconfigurable optimal source detection and beam allocation algorithm (RoSDBA) is proposed. The proposed algorithm is able to allocate desired signal to the user space to reduce the noise and also for efficient allocation of subspace to remove disturbance in all directions. The proposed method efficiently utilizes the antenna array elements by accurate identification and allocation of antenna array elements such as individual radiators, radiation beam, signal strength, and disturbance factor. With respect to simulation analysis, the proposed method shows better performance for the resolution, radiation beam allocations, identification bias, distribution factor and time taken for the detection of various array arrangements and source numbers.
An efficient reconfigurable code rate cooperative low-density parity check codes for gigabits wide code encoder/decoder operations Venkatesh, Divyashree Yamadur; Mallikarjunaiah, Komala; Srikantaswamy, Mallikarjunaswamy
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 6: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i6.pp6369-6377

Abstract

In recent days, extensive digital communication process has been performed. Due to this phenomenon, a proper maintenance of authentication, communication without any overhead such as signal attenuation code rate fluctuations during digital communication process can be minimized and optimized by adopting parallel encoder and decoder operations. To overcome the above-mentioned drawbacks by using proposed reconfigurable code rate cooperative (RCRC) and low-density parity check (LDPC) method. The proposed RCRC-LDPC is capable to operate over gigabits/sec data and it effectively performs linear encoding, dual diagonal form, widens the range of code rate and optimal degree distribution of LDPC mother code. The proposed method optimize the transmission rate and it is capable to operate on 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. the proposed method's implementation has been carried out using MATLAB and as per the simulation result, the proposed method is capable of reaching a throughput efficiency greater than 8.2 (1.9) gigabits per second with a clock frequency of 160 MHz.
An efficient reconfigurable geographic routing congestion control algorithm for wireless sensor networks Pandith, Mamatha M.; Ramaswamy, Nataraj Kanathur; Srikantaswamy, Mallikarjunaswamy; Ramaswamy, Rekha Kanathur
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 6: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i6.pp6388-6398

Abstract

In recent times, huge data is transferred from source to destination through multi path in wireless sensor networks (WSNs). Due to this more congestion occurs in the communication path. Hence, original data will be lost and delay problems arise at receiver end. The above-mentioned drawbacks can be overcome by the proposed efficient reconfigurable geographic routing congestion control (RgRCC) algorithm for wireless sensor networks. the proposed algorithm efficiently finds the node’s congestion status with the help queue length’s threshold level along with its change rate. Apart from this, the proposed algorithm re-routes the communication path to avoid congestion and enhances the strength of scalability of data communication in WSNs. The proposed algorithm frequently updates the distance between the nodes and by-pass routing holes, common for geographical routing. when the nodes are at the edge of the hole, it will create congestion between the nodes in WSNs. Apart from this, more nodes sink due to congestion. it can be reduced with the help of the proposed RgRCC algorithm. As per the simulation analysis, the proposed work indicates improved performance in comparison to conventional algorithm. By effectively identifying the data congestion in WSNs with high scalability rate as compared to conventional methods
An efficient hydro-crop growth prediction system for nutrient analysis using machine learning algorithm Chikkasiddaiah, Chandana; Govindaswamy, Parthasarathy; Srikantaswamy, Mallikarjunaswamy
International Journal of Electrical and Computer Engineering (IJECE) Vol 13, No 6: December 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v13i6.pp6681-6690

Abstract

The hydro nutrient management (HNM) for crop yield is effectively improved using proposed system. A hydro-crop growth prediction system (HCGPS) is designed using machine learning. The reconfigurable nutrients uptake crop yield prediction rate is enhanced. This proposed HCGPS is used to predict the crop yield by considering input parameters such as nutrient index (NI), electric conductivity limit (ECL), ion concentration factors (ICF) and dry weight of the crop and crop yield rate (CYR) to analyze the positive and negative correlation with crop growth. The proposed system is used to find correlation Index of input and output parameters to determine the prediction rate of crop yield. The proposed design improves smart prediction rate and efficiency of crop growth rate with optimal utilization of input variables. This proposed HCGPS is very helpful to achieve good quality yield with optimal utilization of input parameters.
An efficient unused integrated circuits detection algorithm for parallel scan architecture Sathyanarayana, Rekha; Kanathur Ramaswamy, Nataraj; Srikantaswamy, Mallikarjunaswamy; Kanathur Ramaswamy, Rekha
International Journal of Electrical and Computer Engineering (IJECE) Vol 14, No 1: February 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v14i1.pp469-478

Abstract

In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm.
Co-Authors Chikkasiddaiah, Chandana Goravi Sukumar, Pavithra Govindaswamy, Parthasarathy Gowda Puttaswamy, Nandini Honnegowda, Jyothi Hosakote Shankara, Kavitha Kanathur Ramaswamy, Nataraj Kanathur Ramaswamy, Rekha Krishnaiah, Modugu Mallikarjunaiah, Komala Nagaraju, Sharmila Pandith, Mamatha M. Ramaswamy, Nataraj Kanathur Ramaswamy, Rekha Kanathur Sathyanarayana, Rekha Satish, Pooja Shankara, Kavitha Hosakote Thazeen, Sadiya Velluri, Rekha Venkatesh, Divyashree Yamadur