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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
En-Naoui, Ilias
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Control & Systems Engineering Electrical & Electronics Engineering

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DSP implementation and discretization of phase locked loop methods in presence of grid imperfections En-Naoui, Ilias; Radouane, Abdelhadi; Mouhsen, Azeddine; Jarmouni, Ezzitouni; Ennajih, Elmehdi
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 15, No 3: September 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v15.i3.pp1490-1498

Abstract

The fluctuation of grid variables affects the performance of the phase-locked loop, considerably reducing the efficiency of grid energy injection or compensation currents generation during active filtering. The phase locked loop is the main tool for grid synchronization, offering continuous, real-time extraction of grid variables. As these techniques are implemented on digital computers, their discretization and analysis of resource requirements is an important step. This work represents a discretization and implementation on a digital signal processing (DSP) board of two distinct phase-locked loop (PLL) techniques as well as a comparative study of the latter. Our study covers various aspects, including the discretization of the PLLs to be studied, an assessment of the hardware resources required, their implementation on a DSP board, and their effectiveness in quickly identifying grid variables in the presence of imbalance and harmonics, which represent the most frequent grid imperfections.
Design and DSP-based validation of a cascaded DSOGI-PLL for mitigating grid disturbances En-Naoui, Ilias; Radouane, Abdelhadi; Mouhsen, Azeddine; Yantour, Hamid
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 16, No 4: December 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v16.i4.pp2605-2614

Abstract

Ensuring a smooth power injection into an electric grid in the presence of imperfections, such as phase disturbances, voltage imbalance, frequency variations, harmonics, and DC offsets, requires fast and robust phase-locked loop (PLL) techniques. Among these, the double second-order generalized integrator (DSOGI)-based PLL is widely used due to its strong performance in challenging grid conditions. However, conventional DSOGI-PLL has limitations in handling DC offsets and harmonic disturbances. To address these challenges, this paper introduces the design of a cascaded DSOGI-PLL that enhances attenuation of DC components and low-order harmonics while maintaining computational simplicity for DSP-based implementation. Experimental validation on a TMS320F28379D DSP platform demonstrates that the proposed scheme achieves synchronization settling within 48 ms even under severely polluted grid conditions, while reducing output unit-vector THD to 0.5% when the input voltage contains 22% THD. These results confirm the cascaded DSOGI-PLL as a significant improvement over conventional PLLs.
Co-Authors Ennajih, Elmehdi Jarmouni, Ezzitouni Mouhsen, Azeddine Radouane, Abdelhadi Yantour, Hamid