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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
Yantour, Hamid
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Control & Systems Engineering Electrical & Electronics Engineering

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Design and DSP-based validation of a cascaded DSOGI-PLL for mitigating grid disturbances En-Naoui, Ilias; Radouane, Abdelhadi; Mouhsen, Azeddine; Yantour, Hamid
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 16, No 4: December 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v16.i4.pp2605-2614

Abstract

Ensuring a smooth power injection into an electric grid in the presence of imperfections, such as phase disturbances, voltage imbalance, frequency variations, harmonics, and DC offsets, requires fast and robust phase-locked loop (PLL) techniques. Among these, the double second-order generalized integrator (DSOGI)-based PLL is widely used due to its strong performance in challenging grid conditions. However, conventional DSOGI-PLL has limitations in handling DC offsets and harmonic disturbances. To address these challenges, this paper introduces the design of a cascaded DSOGI-PLL that enhances attenuation of DC components and low-order harmonics while maintaining computational simplicity for DSP-based implementation. Experimental validation on a TMS320F28379D DSP platform demonstrates that the proposed scheme achieves synchronization settling within 48 ms even under severely polluted grid conditions, while reducing output unit-vector THD to 0.5% when the input voltage contains 22% THD. These results confirm the cascaded DSOGI-PLL as a significant improvement over conventional PLLs.
Co-Authors En-Naoui, Ilias Mouhsen, Azeddine Radouane, Abdelhadi