International Journal of Power Electronics and Drive Systems (IJPEDS)
Vol 16, No 4: December 2025

Design and DSP-based validation of a cascaded DSOGI-PLL for mitigating grid disturbances

En-Naoui, Ilias (Unknown)
Radouane, Abdelhadi (Unknown)
Mouhsen, Azeddine (Unknown)
Yantour, Hamid (Unknown)



Article Info

Publish Date
01 Dec 2025

Abstract

Ensuring a smooth power injection into an electric grid in the presence of imperfections, such as phase disturbances, voltage imbalance, frequency variations, harmonics, and DC offsets, requires fast and robust phase-locked loop (PLL) techniques. Among these, the double second-order generalized integrator (DSOGI)-based PLL is widely used due to its strong performance in challenging grid conditions. However, conventional DSOGI-PLL has limitations in handling DC offsets and harmonic disturbances. To address these challenges, this paper introduces the design of a cascaded DSOGI-PLL that enhances attenuation of DC components and low-order harmonics while maintaining computational simplicity for DSP-based implementation. Experimental validation on a TMS320F28379D DSP platform demonstrates that the proposed scheme achieves synchronization settling within 48 ms even under severely polluted grid conditions, while reducing output unit-vector THD to 0.5% when the input voltage contains 22% THD. These results confirm the cascaded DSOGI-PLL as a significant improvement over conventional PLLs.

Copyrights © 2025






Journal Info

Abbrev

IJPEDS

Publisher

Subject

Control & Systems Engineering Electrical & Electronics Engineering

Description

International Journal of Power Electronics and Drive Systems (IJPEDS, ISSN: 2088-8694, a SCOPUS indexed Journal) is the official publication of the Institute of Advanced Engineering and Science (IAES). The scope of the journal includes all issues in the field of Power Electronics and drive systems. ...