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International Journal of Electrical and Computer Engineering

IJECE
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Published by Institute of Advanced Engineering and Science

ISSN : 20888708 EISSN : 27222578 DOI : -

Core Subject : Science, Engineering,

Computer Science & IT Electrical & Electronics Engineering

International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of Advanced Engineering and Science (IAES). The journal is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the global world.

Arjuna Subject : Ilmu Komputer (semua kategori) - Ilmu Komputer (Lain-Lain)

Articles 6,301 Documents

142 143 144 145 146

Solving Task Scheduling Problem in Cloud Computing Environment Using Orthogonal Taguchi-Cat Algorithm Danlami Gabi; Abdul Samad Ismail; Anazida Zainal; Zalmiyah Zakaria
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 3: June 2017
Publisher : Institute of Advanced Engineering and Science

In cloud computing datacenter, task execution delay is no longer accidental. In recent times, a number of artificial intelligence scheduling techniques are proposed and applied to reduce task execution delay. In this study, we proposed an algorithm called Orthogonal Taguchi Based-Cat Swarm Optimization (OTB-CSO) to minimize total task execution time. In our proposed algorithm Taguchi Orthogonal approach was incorporated at CSO tracing mode for best task mapping on VMs with minimum execution time. The proposed algorithm was implemented on CloudSim tool and evaluated based on makespan metric. Experimental results showed for 20VMs used, proposed OTB-CSO was able to minimize makespan of total tasks scheduled across VMs with 42.86%, 34.57% and 2.58% improvement over Minimum and Maximum Job First (Min-Max), Particle Swarm Optimization with Linear Descending Inertia Weight (PSO-LDIW) and Hybrid Particle Swarm Optimization with Simulated Annealing (HPSO-SA) algorithms. Results obtained showed OTB-CSO is effective to optimize task scheduling and improve overall cloud computing performance with better system utilization.

The new integer factorization algorithm based on Fermat’s Factorization Algorithm and Euler’s theorem Kritsanapong Somsuk
International Journal of Electrical and Computer Engineering (IJECE) Vol 10, No 2: April 2020
Publisher : Institute of Advanced Engineering and Science

Although, Integer Factorization is one of the hard problems to break RSA, many factoring techniques are still developed. Fermat’s Factorization Algorithm (FFA) which has very high performance when prime factors are close to each other is a type of integer factorization algorithms. In fact, there are two ways to implement FFA. The first is called FFA-1, it is a process to find the integer from square root computing. Because this operation takes high computation cost, it consumes high computation time to find the result. The other method is called FFA-2 which is the different technique to find prime factors. Although the computation loops are quite large, there is no square root computing that included into the computation. In this paper, the new efficient factorization algorithm is introduced. Euler’s theorem is chosen to apply with FFA to find the addition result between two prime factors. The advantage of the proposed method is that almost of square root operations are left out from the computation while loops are not increased, they are equal to the first method. Therefore, if the proposed method is compared with the FFA-1, it implies that the computation time is decreased, because there is no the square root operation and the loops are same. On the other hand, the loops of the proposed method are less than the second method. Therefore, time is also reduced. Furthermore, the proposed method can be also selected to apply with many methods which are modified from FFA to decrease more cost.

A Compact Planar Low-Pass Filter Based on SRR-Metamateria Badr Nasiri; Ahmed Errkik; Jamal Zbitou; Abdelali Tajmouati; Larbi El Abdellaoui; Mohamed Latrach
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

In this work, a novel design of a Microstrip Low-pass filter based on metamaterial square split ring resonators (SRRs) is proposed. The SRRs has been added to obtain a reduced size and high performances. The filter is designed on an FR-4 substrate having a thickness of 1.6mm, a dielectric constant of 4.4 and loss tangent of 0.025. The proposed low-pass filter is characterized by a cutoff frequency of 2.4 GHz and an attenuation level below than -20dB in the stopband. The LPF is designed, simulated and optimized by using two electromagnetic solvers CST microwave studio and ADS. The computed results obtained by both solvers are in good agreement. The total surface area of the proposed circuit is 18x18mm2 excluding the feed line, its size is miniaturized by 40% compared to the conventional filter. The experimental results illustrate that the filter achieves very good electrical performances in the passband with a low insertion loss of 0.2 dB. Moreover, a suppression level can reach more than 35 dB in the rejected band.

Implementation of High Security Cryptographic System with Improved Error Correction and Detection Rate using FPGA Narendra Babu T; Fazal Noorbasha; Leenendra Chowdary Gunnam
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 2: April 2016
Publisher : Institute of Advanced Engineering and Science

In this article, an encryption algorithm with an error detection technique is presented for highly secured reliable data transmission over unreliable communication channels. In this algorithm, an input data is mapped into orthogonal code first. After that the code is encrypted with the help of Linear Feedback Shift Register (LFSR). The technique has been successfully verified and synthesized using Xilinx by Spartan-3E FPGA. The results show that the error detection rate has been increased to 100% by proposed encryption scheme is effective and improves bandwidth efficiency.

A Modular Approach and Simulation of an Asynchronous Machine Zineb Mekrini; Seddik Bri
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 4: August 2016
Publisher : Institute of Advanced Engineering and Science

This article presents the modeling and simulation of the asynchronous machine. The aim of this research is the mastery of the electrical, mechanical and magnetic behaviors of this type of machine. The Matlab/Simulink is used for simulation two types of no-load and additional load services in transitional and permanent operation. The Analytical equations describing the two operating systems are evaluated and developed by a generalized model of a three-phase induction motor. The simulation results presented in this article confirms that the proposed model gave a satisfactory response in terms of torque characteristics and speed.

A Systematic Method for Identification of Anti-patterns in Service Oriented System Development Mohammad Ali Torkamani; Hamid Bagheri
International Journal of Electrical and Computer Engineering (IJECE) Vol 4, No 1: February 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (226.312 KB)

Service-Oriented Architecture is one of the popular software architecture's patterns used for developing lots of modern systems. However, it has been involved in many failures. Anti-patterns are solutions which have good view, but in fact they are wrong solutions that cause failure of systems. There are a lot of anti-patterns for SOA and new anti-patterns are revealed every day. Anti-patterns have their own reasons for being formed and also they are appeared in special area of the problem. As human's mind is restricted and it can process a limited number of states (piece of information) therefore identification of anti-patterns will be difficult for architects. In this paper, we propose a systematic method based on repository of anti-patterns along with a check list to identify anti-patterns of SOA. This method will assist architects to easily detect and avoid anti-patterns in development process and so escape from risks which related to anti-patterns. Furthermore, in this paper, we present a repository of forty five general anti-patterns in SOA. Reviewing these anti-patterns will help developers to work with clear understanding of patterns in phases of software development and so avoid from many potential problems. Also, our method is evaluated in action.DOI:http://dx.doi.org/10.11591/ijece.v4i1.4097

Parallelising reception and transmission in queues of secondary users Lak Sad
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 4: August 2019
Publisher : Institute of Advanced Engineering and Science

In a cognitive radio network, the secondary users place the packets to be transmitted on a queue to control the order of arrival and to adapt to the network state. Previous conceptionsassigned to each secondary user a single queue that contains both received and forwarded packets. Our present article divides the main queue into two sub queues: one to receive the arrived packets and the other to transmit the available packets. This approach reduces the transmission delay due on the one hand; to the shifting of data placed on the single queue, and on the other hand; to the sequential processing of reception and transmission, in theprevious designs. All without increasing the memory capacity of the queue, in the new approach.

A Novel Three Phase Multilevel Inverter with Single Dc Link For Induction Motor Drive Applications A. Ramesh; O. Chandra Sekhar; M. Siva Kumar
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 2: April 2018
Publisher : Institute of Advanced Engineering and Science

All industrial drives need a controlled output and it can be achieved by controlling the input supply. In this regard, the inverter circuit plays an important role in the applications of industrial drives. The industrial drives are operated at high rated power and the conventional inverters cannot be applicable for high power demands because of the large dV/dt (rate of change of voltage) and more switching losses. Therefore, multilevel inverters are introduced for high power-medium voltage applications. For all AC drives the MLIs are reliable in operation. This MLI topology also reduces the harmonics and bearings stress of a motor with low dV/dt. In most applications multilevel inverters are used because we can get more number of voltage levels. To increase the number of voltage levels, circuit needs to have more switches. But, we have to optimize the switch count and switching operations. The power level of the inverter is limited due to high currents and stress. In this paper, we proposed a new circuit topology which enables the switches to be active at different voltage levels, causes reduction of the switching losses and also increases the efficiency of the inverter. In this we have presented two configurations for an eleven level MLI for three phase induction motor drive application. In this an individual DC source is connected for each bridge circuit of each phase in one configuration and only one common DC link is used for three phases in another configuration. With this the size, cost and complexity could be decreased. In both the configurations the controlled output of the inverter is connected to the induction motor drive. The circuits are modeled using Matlab/simulink software and corresponding output waveforms are analyzed for both configurations.

Misusability Measure Based Sanitization of Big Data for Privacy Preserving MapReduce Programming D. Radhika; D. Aruna Kumari
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 6: December 2018
Publisher : Institute of Advanced Engineering and Science

Leakage and misuse of sensitive data is a challenging problem to enterprises. It has become more serious problem with the advent of cloud and big data. The rationale behind this is the increase in outsourcing of data to public cloud and publishing data for wider visibility. Therefore Privacy Preserving Data Publishing (PPDP), Privacy Preserving Data Mining (PPDM) and Privacy Preserving Distributed Data Mining (PPDM) are crucial in the contemporary era. PPDP and PPDM can protect privacy at data and process levels respectively. Therefore, with big data privacy to data became indispensable due to the fact that data is stored and processed in semi-trusted environment. In this paper we proposed a comprehensive methodology for effective sanitization of data based on misusability measure for preserving privacy to get rid of data leakage and misuse. We followed a hybrid approach that caters to the needs of privacy preserving MapReduce programming. We proposed an algorithm known as Misusability Measure-Based Privacy serving Algorithm (MMPP) which considers level of misusability prior to choosing and application of appropriate sanitization on big data. Our empirical study with Amazon EC2 and EMR revealed that the proposed methodology is useful in realizing privacy preserving Map Reduce programming.

Human Data Acquisition through Biometrics using LabVIEW K Nishanth Rao; N. Vasudheva Reddy
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 1: February 2017
Publisher : Institute of Advanced Engineering and Science

Human Data Acquisition is an innovative work done based on fingerprints of a particular person. Using the fingerprints we can get each and every detail of any individual. Through this, the data acquired can be used in many applications such as Airport Security System, Voting System, and Employee login System, in finding the thieves etc. We in our project have implemented in Voting System. In this we use the components such as MyDAQ which is data acquisition device. The coding here is in done in a Graphical Programming language named LabVIEW where the execution of any program is done in a sequential way or step by step according to the data received.

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Tole Sutikno

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Daerah istimewa yogyakarta

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Home Page

OAI Link

Editorial Team

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Reviewer

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Contact Name Tole Sutikno

Contact Email ijece@iaesjournal.com

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Journal Mail Official ijece@iaesjournal.com

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Location Kota yogyakarta, Daerah istimewa yogyakarta INDONESIA

Abstract

Abstract

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Abstract

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Abstract

Contact Name
Tole Sutikno

Contact Email
ijece@iaesjournal.com

Phone
-

Journal Mail Official
ijece@iaesjournal.com

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA