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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 30 Documents
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Search results for , issue "Vol 14, No 1: March 2025" : 30 Documents clear
Implementation of flexible axis photovoltaic system based on internet of things Firdaus, Aji Akbar; Daud, Muhamad Zalani; Rajendran, Parvathy; Solihin, Mahmud Iwan; Wang, Li; Azmita, Mimi; Arof, Hamzah
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp157-164

Abstract

Electricity is a crucial aspect in human life. With population growth, ongoing regional development, and continuous construction activities, the demand for electricity and fuel in Indonesia is increasing. The substantial power consumption leads to larger financial expenditures for the community. Additionally, the use of electricity, as it has been traditionally employed, has negative environmental impacts. Solutions are needed to address these issues, and one effort involves the use of renewable energy, such as the development of solar power plants (PLTS). PLTS, also known as solar cells, is preferred as it can be used for various relevant purposes in different locations, particularly in offices, factories, residential areas, and others. However, the use of static, single-axis, and dual-axis solar panels still has drawbacks, such as suboptimal sunlight intensity and high motor power consumption. Therefore, a flexible-axis solar panel tracking system has been developed to follow the direction of sunlight, ensuring optimal power efficiency, and significant electricity generation. The flexible-axis tracker system results in a 34.13% increase in power efficiency.
Implementing a very high-speed secure hash algorithm 3 accelerator based on PCI-express Huynh, Huu-Thuan; Tran, Tuan-Kiet; Dang, Tan-Phat
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp1-11

Abstract

In this paper, a high-performance secure hash algorithm 3 (SHA-3) is proposed to handle massive amounts of data for applications such as edge computing, medical image encryption, and blockchain networks. This work not only focuses on the SHA-3 core as in previous works but also addresses the bottleneck phenomenon caused by transfer rates. Our proposed SHA-3 architecture serves as the hardware accelerator for personal computers (PC) connected via a peripheral component interconnect express (PCIe), enhancing data transfer rates between the host PC and dedicated computation components like SHA-3. Additionally, the throughput of the SHA-3 core is enhanced based on two different proposals for the KECCAK-f algorithm: re-scheduled and sub-pipelined architectures. The multiple KECCAK-f is applied to maximize data transfer throughput. Configurable buffer in/out (BIO) is introduced to support all SHA-3 modes, which is suitable for devices that handle various hashing applications. The proposed SHA-3 architectures are implemented and tested on DE10-Pro supporting Stratix 10 - 1SX280HU2F50E1VG and PCIe, achieving a throughput of up to 35.55 Gbps and 43.12 Gbps for multiple-re-scheduled-KECCAK-f-based SHA3 (MRS) and multiple-sub-pipelined-KECCAK-f-based SHA-3 (MSS), respectively.
Development of internet of vehicles and recurrent neural network enabled intelligent transportation system for smart cities Surve, Jyoti; Bangare, Manoj L.; Bangare, Sunil L.; Pol, Urmila R.; Mali, Manisha; Meenakshi, Meenakshi; Alsalmani, Abdullah; Morsi, Sami A.
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp291-300

Abstract

The number of deaths has increased as a direct result of the increased frequency of traffic accidents, congestion, and other risk factors. Developing countries have prioritised the development of intelligent transport systems in order to reduce pollution, traffic congestion, and wasted time. This article describes an intelligent transport system that leverages the internet of vehicles (IoV) and deep learning to forecast traffic congestion. Data is acquired using a car’s global positioning system (GPS), road and vehicle sensors, traffic cameras, and traffic speed, density, and flow. All acquired data is stored in one location on a cloud server. The cloud server also stores historical traffic, road, and vehicle data. Using particle swarm optimisation, features are improved. The optimised dataset is used to train and test recurrent neural networks (RNNs), support vector machines (SVMs), and multi layer perceptrons (MLPs). A deep learning algorithm can predict traffic congestion and make recommendations to drivers on how fast to travel and which route to take. The experimental effort employs the performance measurement system (PeMS) traffic dataset. RNN has achieved accuracy of 95.1%.
Multimodal recognition with deep learning: audio, image, and text Gummula, Ravi; Arumugam, Vinothkumar; Aranganathan, Abilasha
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp254-264

Abstract

Emotion detection is essential in many domains including affective computing, psychological assessment, and human computer interaction (HCI). It contrasts the study of emotion detection across text, image, and speech modalities to evaluate state-of-the-art approaches in each area and identify their benefits and shortcomings. We looked at present methods, datasets, and evaluation criteria by conducting a comprehensive literature review. In order to conduct our study, we collect data, clean it up, identify its characteristics and then use deep learning (DL) models. In our experiments we performed text-based emotion identification using long short-term memory (LSTM), term frequency-inverse document frequency (TF-IDF) vectorizer, and image-based emotion recognition using a convolutional neural network (CNN) algorithm. Contributing to the body of knowledge in emotion recognition, our study's results provide light on the inner workings of different modalities. Experimental findings validate the efficacy of the proposed method while also highlighting areas for improvement.
Design and implementation of smart traffic light controller with emergency vehicle detection on FPGA Mohamad Hadis, Nor Shahanim; Abdullah, Samihah; Abdul Sukor, Muhammad Ameerul Syafiqie; Hamzah, Irni Hamiza; Setumin, Samsul; Ibrahim, Mohammad Nizam; Azmin, Azwati
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp48-59

Abstract

Increased traffic volumes resulting from urbanization, industrialization, and population growth have given rise to complex issues, including congestion, accidents, and traffic violations at intersections. In the absence of a functional smart traffic light system, traffic congestion occurs due to imbalanced traffic flow at intersections. Current traffic management lacks provisions for ensuring the unobstructed movement of emergency vehicles, even a small delay for which can have significant consequences. This paper presents a smart traffic light controller developed using Verilog hardware description language (HDL) in Quartus Prime 21.1 and Questa Intel field programmable gate array (FPGA) Starter Edition 2021.2, and implemented on an Altera DE2-115 FPGA. The controller is designed specifically to detect emergency vehicle at four-way intersections for inputs radio frequency identification (RFID) readers and infrared (IR) sensors. The RFID readers and IR sensors are managed through slide switches on the FPGA board. The smart traffic light controller contains three sub-modules: clock division, counter, and finite state machine (FSM) operation, enabling it to manage traffic in scenarios with emergency vehicles, high traffic density, and low traffic density. This proposed system can alleviate intersection congestion by controlling access and allocating time effectively. In conclusion, the project ensures the smooth passage of emergency vehicles by continuously monitoring their presence and giving them priority in traffic flow.
Finite element analysis method as an alternative for furniture prototyping process and product testing Kristianto, Fesa Putra; Amarta, Zain; Hutasoit, Nicolas; Fariz, Nuthqy; Herinda, Fania Putri
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp231-242

Abstract

In the current furniture industry, making furniture goes through many steps. There are ordering materials, designing, building a prototype, and testing samples. This process is considered quite complex, requiring significant costs, and lengthy production time. The application of finite element analysis (FEA) can be a solution to simulate the furniture manufacturing process. Objective of this research was to determine FEA could substitute making and test prototype furniture thereby saving costs and time. This method utilizes ANSYS 18.1 software for more accurate and rapid calculations, incorporating load variables of 400 N, 600 N, 800 N, and 1,000 N, along with gravitational acceleration of 10 \frac{m}{s^2}. The research evaluates the difference (expressed as a percentage) between the results obtained from simulations and those obtained directly from experiments, considering maximum equivalent stress, maximum principal stress, and total deformation values. The final step involves comparing the simulation with direct testing in terms of cost and time. The research results show an average error factor of 5% across all aspect. In terms of cost, the method can save 1,807 USD and reduce production time by up to one month. From these findings, it can be concluded that the process of prototyping and sample testing can be replaced using the finite element method.
Comparative analysis of feature descriptors and classifiers for real-time object detection Nandeshwar, Vikas J.; Bhatlawande, Sarvadnya; Solanke, Anjali; Sathe, Harsh; Satao, Shivanand; Satpute, Safalya; Saste, Atharva
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp89-99

Abstract

Detecting objects within complex environments, such as urban settings, holds significant importance across various applications, including driver assistance systems, traffic monitoring, and obstacle detection systems. Particularly crucial for these applications is the accurate differentiation between cars and roads. This study introduces a novel approach that leverages traditional feature descriptors and classifiers for real-time object detection. It conducts an exhaustive comparative analysis of feature descriptors and classifiers to identify the most effective model for real-time object detection. Handcrafted features of images are extracted using algorithms such as scale invariant feature transform (SIFT), oriented fast and brief (ORB), fast retina key-point (FREAK), and local binary pattern (LBP). Seven classifiers are employed, including support vector machine (SVM), K-nearest neighbors (KNN), random forest (RF), decision tree (DT), logistic regression (LR), Naive Bayes, and extreme gradient boosting (XGBoost). The performance of the 28 generated combinations of feature descriptors and classifiers is evaluated based on the parameters of accuracy, precision, F1 score, and recall. The model utilizing LBP and XGBoost achieves the highest accuracy, reaching 83.59%. The system architecture comprises a camera, a high-speed computing unit, a display, and an audio subsystem, with the algorithm implemented on a Raspberry Pi 4B (8 GB).
Comparative analysis of ZigBee, LoRa, and NB-IoT in a smart building: advantages, limitations, and integration possibilities Inthasuth, Tanakorn; Kaewjumras, Yongyut; Somwong, Sahapong; Boonsong, Wasana
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp165-175

Abstract

This paper compares the performance of various wireless technologies: ZigBee, long range (LoRa), and narrowband internet of things (NB-IoT), which support smart building applications. The highlight of this work is that we focus on wireless communication between the floors of the building by analyzing the performance metrics using the received signal strength indicator (RSSI) and packet loss ratio (PLR). First, the ZigBee tests confirmed reliable packet delivery without any loss over distances up to 40 meters on the same floor, with RSSI results ranging from -65.5 to -87.5 dBm. ZigBee also maintained signal transmission through one cross-floor level, with RSSI values between -60 and -119 dBm. The second set of tests, with LoRa, indicated signal transmission over several floors with slightly improved RSSI values for the 2 dBi antenna compared to those for the -4 dBi antenna, despite increased packet loss with distance. Finally, NB-IoT showed the most consistent long-range connectivity, achieving a stable signal up to 458 meters from the base station with RSSI levels varying from -55.6 to -74.6 dBm, without packet loss in all tests. This study demonstrates how such technologies could be used in smart buildings and provides suggestions on how to determine the most suitable systems and configure them to ensure reliable communication networks within the building.
Artificial intelligence driven robotic control system for personalized elderly care and foot massage Bhatlawande, Shripad; Shilaskar, Swati; Akotkar, Soham; Joshi, Anish; Ansari, Zayd
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp35-47

Abstract

This research presents an electronic system for providing foot massage to the elderly, along with artificial intelligence (AI) driven voice-controlled conversation bot. The problem under study focuses on the elderly age group suffering from foot related ailments, most commonly foot pain. Also, the risk of depression or anxiety is high for this age group due to social isolation. These problems are addressed by the system under discussion integrated with a voice assistant to converse with the elderly. The AI assisted conversation bot enables the elderly to make customized reminders for their timely medications and provides general updates on essential topics. The system extends to provide the elderly, foot, and calf massage controlled with mobile application. It consists of a low power motor arrangement along with a high computing system. The electronic system was subjected to trials on elderly for verification and validation of the system to assess its ability of providing users with appropriate assistance. The trials were conducted on twenty elderly, aged sixty, and above, living self-sufficiently with foot related ailment. All elderly were subjected to the conversation bot along with the foot and calves’ massage, providing subjective feedback on the system's ability to enhance their quality of life. The subjective feedback after quantification have demonstrated the ability of the system in improving their living standards.
A fast half-subtractor using 8T static random access memory for in-memory computation Prabhakar, Deepika; Shylashree, Nagaraja; Narasimhaiah, Sunitha Yariyur; Mariswamappa, Yashaswini Biligere; Hemaraj, Sheetal Singrihalli
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp273-281

Abstract

The existing system for computation completely incorporates Von-Neumann architecture which has limitations with respect to its memory, parallelism and power constraints. This has affected the efficiency of the computing system. Novel architectural solutions are required to meet the growing demands for improved computational efficiency and power management in very large scale integration (VLSI) systems. To deal with the large-scale data, computation in memory (CIM) has been introduced. The paper presents the half subtractor circuit and the In-memory computation co-design using eight transistors static random access memory (SRAM) cell whose read circuitry is transmission gate based. The proposed half-subtractor with the CIM is implementation is carried out in 180 nm complementary metal– oxide–semiconductor (CMOS) technology. The sensing scheme used is the latch-based sense amplifier along with the 8T SRAM cell. The proposed SRAM with transmission-gate based read circuitry along with latch-based sense amplifier reduces the delay and power consumed during the read operation significantly and a bit reduction during the write operation. The static noise margin (SNM) for read operation has been increased by 9% in the transmission gate-based SRAM as compared to conventional 8T SRAM. The delay of the proposed design has been reduced by 53% during the read operation and 4.43% during the write operation. The power consumed has been reduced by 3% and 8.6% during read and write operations, respectively.

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