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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 27 Documents
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Search results for , issue "Vol 14, No 2: July 2025" : 27 Documents clear
FPGA-based implementation of a substitution box cryptographic co-processor for high-performance applications Ahmed Nassim, Moulai Khatir; Zakarya, Ziani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp587-596

Abstract

The increasing demand for reliable cryptographic operations for securing current systems has given birth to well-advanced and developed hardware solutions, in this paper we consider issues within the traditional symmetric advanced encryption standard (AES) cryptographic system as major challenges. Additionally, problems such as throughput limitations, reliability, and unified key management are also discussed and tackled through appropriate hierarchical transformation techniques. To overcome these challenges, this paper presents the design and field programmable gate array (FPGA)-based implementation of a cryptographic coprocessor optimized for substitution box (S-Box) operation which is considered as a key component in many cryptographic algorithms such as AES. The architecture of the co-processor proposed in this article is based on the advanced characteristics of FPGAs to accelerate the S-Box transformation, improve throughput and reduce latency compared to software implementations. We discussed carefully the design considerations along with resource utilization, speed optimization, and energy efficiency. The obtained experimental results present significant performance improvements, the FPGA-based implementation ensured higher throughput and lower execution time compared to traditional central processing unit (CPU)-based methods. We presented in this work the effectiveness of using FPGAs for the acceleration of cryptographic operations in secure applications which will therefore be a robust solution for the next generation of secure systems.
Development of a web-based application for real-time eye disease classification system using artificial intelligence Okokpujie, Kennedy; Tolulope, Adekoya; Orimogunje, Abidemi; Mommoh, Joshua Sokowonci; Ijeh, Adaora Princess; Ogundele, Mary Oluwafeyisayo
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp558-574

Abstract

The incorporation of artificial intelligence (AI) into the field of medicine has created new strategies in enhancing the detection of disease, with a focus on the identification of eye diseases such as glaucoma, diabetic retinopathy, and macular degeneration associated with age, which can lead to blindness if not detected and treated early enough. Driven by the need to combat blindness, which affects approximately 39 million people globally, according to the World Health Organization (WHO). This research offers a web-based, real time approach to classifying eye diseases from fundus images due to user friendliness. Three pre-trained convolutional neural network (CNN) models are adopted, namely ResNet-50, Inception-v3, and MobileNetV3. The models were trained on a dataset of 8000 fundus images subdivided into four classes: cataract, glaucoma, diabetic retinopathy, and normal eyes. The performance of the models was evaluated in 3-way (normal eye and two diseases) and 4-way (normal eye and three diseases). ResNet-50 had higher performances, with 98% and 97% accuracy in the respective classifications, compared to InceptionV3 and MobileNetV3. Consequently, ResNet-50 was used in an online application that made real-time diagnoses. This research findings reveal the potential of CNNs in the healthcare industry, particularly in reducing over-reliance on specialists and increasing access to quality diagnostic technologies. Especially in critical areas such as this with limited healthcare resources, where the technology can create significant gaps in disease detection and control.
A novel approach to transparent and accurate fuel dispensing for consumer protection Phade, Gayatri; Ohatkar, Sharada Narsingrao; Pushpavalli, Murugan; Chitre, Vidya; Pawar, Vijaya; Vaidya, Omkar Suresh; Ramachandran, Harikrishnan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp353-364

Abstract

Consumer rights are exploited around the world and it is necessary for to protect consumer rights by means of safeguarding consumers from various unfair trade practices. Those most vulnerable to such exploitation must be shielded, and this is achieved through consumer protection measures. One such example of unethical behavior is fuel stealing at fuel stations. To overcome this critical issue, a low-cost fuel quantity sensing and monitoring system is proposed in this paper. A fuel detection system will ensure the exact quantity of fuel filled in fuel tank and will detect fuel theft, if any, at fuel pumps. An embedded system is developed for this purpose, consisting of sensors, display devices, communication devices and microcontroller. The quantity of fuel filled in the tank is transmitted to mobile phone of the consumer to avoid fuel theft. Performance of the system is validated by comparing the displayed amount of fuel dispensed and actual filled in the tank and achieve 99.95% accuracy. With this consumer right to get the value for amount paid for the petrol will be protected. This novel feature can be added in the fuel tank of the smart vehicle development and design as a future scope.
An optimized simulated annealing memetic algorithm for power and wirelength minimization in VLSI circuit partitioning Rajeswari, P.; Sasi, Smitha
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp365-374

Abstract

The development of physical architecture standards for very large scale integration (VLSI) single and multichip platforms is still in its early stages. To deal with the growing complexity of modern VLSI systems, it has become common practice to split large circuit architectures into smaller, easier-to-manage sub-circuits. Circuit partitioning improves parallel modeling, testing, and system performance by lowering chip size, number of components and interconnects, wire length (WL), and delays. VLSI partitioning's primary goal is to split a circuit into smaller blocks with as few connections as possible between them. This is frequently accomplished by recursive bi-partitioning until the required complexity level is reached. Thus, partitioning is a fundamental circuit design challenge. An efficient remedy that offers a heuristic method that explores the design space to iteratively enhance outcomes is evolutionary computation. In order to minimize WL, area, and interconnections, we provide an optimized simulated annealing memetic algorithm (OSAMA) that combines local search methods with evolutionary tactics. The efficiency of the method was evaluated using criteria like runtime, cost, delay, area, and WL. OSAMA's ability for effective partitioning is demonstrated by experimental results, which confirm that it dramatically lowers important design parameters in VLSI circuits.
Building a photonic neural network based on multi-operand multimode interference ring resonators Do, Thanh Tien; Pham, Hai Yen; Thanh, Trung
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp311-319

Abstract

Photonic neural networks (PNNs) offer significant potential for enhancing deep learning networks, providing high-speed processing and low energy consumption. In this paper, we present a novel PNN architecture that employs nonlinear optical neurons using multi-operand 4×4 multimode interference (MMI) multi-operand ring resonators (MORRs) to efficiently perform vector dot-product calculations. This design is integrated into a photonic convolutional neural network (PCNN) with two convolutional layers and one fully connected layer. Simulation experiments, conducted using Lumerical and Ansys tools, demonstrated that the model achieved a high test accuracy of 98.26% on the MNIST dataset, with test losses stabilizing at approximately 0.04%. The proposed model was evaluated, demonstrating high computation speed, improved accuracy, low signal loss, and scalability. These findings highlight the model’s potential for advancing deep learning applications with more efficient hardware implementations.
Enhancing intrusion detection systems with hybrid HHO-WOA optimization and gradient boosting machine classifier Abualhaj, Mosleh M.; Abu-Shareha, Ahmad Adel; Rateb, Roqia
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp518-526

Abstract

In this paper, we propose a hybrid intrusion detection system (IDS) that leverages Harris Hawks optimization (HHO) and whale optimization algorithm (WOA) for feature selection to enhance the detection of cyberattacks. The hybrid approach reduces the dimensionality of the NSL KDD dataset, allowing the IDS to operate more efficiently. The reduced feature set is then classified using logistic regression (LR) and gradient boosting machine (GBM) classifiers. Performance evaluation demonstrates that the GBM-HHO/WOA combination outperforms the LR-HHO/WOA approach, achieving an accuracy of 97.68%. These results indicate that integrating HHO and WOA significantly improves the IDS's ability to identify intrusions while maintaining high computational efficiency. This research highlights the potential of advanced optimization techniques to strengthen network security against evolving threats.
An approximate model SpMV on FPGA assisting HLS optimizations for low power and high performance Shaji, Alden C.; Aizaz, Zainab; Khare, Kavita
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp375-387

Abstract

High performance computing (HPC) in embedded systems is particularly relevant with the rise of artificial intelligence (AI) and machine learning at the edge. Deep learning models require substantial computational power, and running these models on embedded systems with limited resources poses significant challenges. The energy-efficient nature of field-programmable gate arrays (FPGAs), coupled with their adaptability, positions them as compelling choices for optimizing the performance of sparse matrix-vector multiplication (SpMV), which plays a significant role in various computational tasks within these fields. This article initially did analysis to find a power and delay efficient SpMV model kernel using high level synthesis (HLS) optimizations which incorporates loop pipelining, varied memory access patterns, and data partitioning strategies, all of this exert influence on the underlying hardware architecture. After identifying the minimum resource utilization model, we propose an approximate model algorithm on SpMV kernel to reduce the execution time in Xilinx Zynq-7000 FPGA. The experimental results shows that the FPGA power consumption was reduced by 50% when compared to a previously implemented streaming dataflow engine (SDE) flow, and the proposed approximate model improved performance by 2× times compared to that of original compressed sparse row (CSR) sparse matrix.
Design and structural modelling of patient-specific 3D-printed knee femur and tibia implants Sandeep, Bolugoddu; Dhanushkodi, Saravanan; Kumarasamy, Sudhakar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp575-586

Abstract

Arthritis is a degenerative joint condition that progressively damages the knee, leading to pain, stiffness, and limited mobility. To alleviate these symptoms and restore joint functionality, total knee arthroplasty (TKA) is performed. This procedure becomes necessary due to either sudden trauma to the knee or gradual wear and tear of the meniscus and cartilage. TKA involves meticulous planning, precise bone cutting, and the placement of prosthetic components made from high-density polyethylene and metal alloys. However, traditional methods creating customized knee implants are expensive and time-intensive. This study explores the challenges in manufacturing personalized knee implants for TKA and evaluates the potential of three-dimensional (3D) printing technology in this process. Variations in knee joint anatomy across populations complicate surgery, as optimal outcomes rely on precise alignment and implant dimensions. A preoperative computed tomography (CT) scan identifies the region of interest (ROI), such as the knee joint. The scan data is then processed using computer-aided design (CAD) software to generate a printable file. The patient’s CT scan data is converted into a standard triangulation language (STL) file and CAD models of the knee joint. Errors such as overlapping triangles or open loops in the STL file are corrected, and unwanted geometries near the ROI are removed. Resection techniques are applied to create CAD models tailored to the patient’s bone morphology. Fused deposition modeling (FDM) is then used to produce prototypes of the knee joint and implants. Despite visible layer lines in the printed prototypes, challenges encountered during the process were effectively resolved.
A custom reduced instruction set computer-V based architecture for real-time electrocardiogram feature extraction Shinde, Vinayak Vikram; Bhandari, Sheetal Umesh; Khurge, Deepti Snehal; Nagarale, Satyashil Dasharath; Shirode, Ujwal Ramesh
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp412-427

Abstract

The growing demand for energy-efficient and real-time biomedical signal processing in wearable devices has necessitated the development of application-specific and reconfigurable embedded hardware architectures. This paper presents the register transfer level (RTL) design and simulation of a custom reduced instruction set computer-V (RISC-V) based hardware architecture tailored for real-time electrocardiogram (ECG) feature extraction, focusing on R-peak detection and heart rate (HR) calculation. The proposed system combines ECG-specific functional blocks including a specialized ECG arithmetic logic unit and a finite state machine-based ECG control unit with a compact 16-bit RISC-V control core. Hardware optimized algorithms are used to carry out pre-processing activities such high-pass and low-pass filtering as well as feature extraction processes including moving average filtering, derivative calculation, and threshold based peak identification. Designed to reduce memory footprint and control complexity, a custom instruction set architecture supports modular reconfigurability. Functional validation is carried out by Xilinx Vivado simulating RTL components described in very high speed integrated circuit (VHSIC) hardware description language (VHDL). The present work shows successful simulation of important architectural components, complete system-level integration and custom ECG data validation. This work provides the basis for an application-specific, reconfigurable, power efficient hardware solution for embedded health-monitoring devices.
Enhanced fault detection in photovoltaic systems using an ensemble machine learning approach Ibrahim, Mohammed Salah; Almulla, Hussein k.; Sallibi, Anas D.; Nafea, Ahmed Adil; Kareem, Aythem Khairi; Alheeti, Khattab M. Ali
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp507-517

Abstract

Malfunctioning of photovoltaic (PV) systems is a main issue affecting solar panels and other related components. Detecting such issues early leads to efficient energy production with low maintenance costs and high system performance consistency. This paper proposed an ensemble model (EM) for fault detection (FD) in PV systems. The proposed model utilized advanced machine learning algorithms containing random forest (RF), k-nearest neighbors (KNN), and gradient boosting (GB). Traditional approaches often do not handle the several situations that PV systems can have. Our EM leveraged the power of GB’s algorithm in handling complex data patterns through iterative boosting, KNN’s capability in capturing local data structures, and RF’s strength in handling overfitting and noise through its tree structure randomness. Combining these models enhanced fault detection capabilities, providing excellent accuracy compared to individual models. To evaluate the performance of our EM, different experiments were conducted. The results demonstrated substantial improvements in detection fault, achieving an accuracy rate of 95%. This accuracy rate considered high underscores the model’s capability to handle fault detection of PV systems, posing a consistent solution for instant fault detection and maintenance scheduling.

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