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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 479 Documents
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Synaptic shield: fusion of ResNext–50 and long short-term memory for enhanaced deepfake detection Mishra, Amit; Chinchmalatpure, Prajwal; Sambare, Govinda B.; Singh, Viomesh Kumar; Pawar, Atul Gulabrao; Mirajkar, Rahul Prakash; Takalkar, Priyanka K.; Vayadande, Kuldeep
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp224-235

Abstract

Recent developments in deepfakes have created much anxiety about the authenticity of any digital content and thus, calls for implementing detection mechanisms that will work accordingly. This paper uses Synaptic Shield, a innovative deep learning (DL) framework which is customized to detect alterations by deepfakes with high precision levels. It employs both convolution neural networks (CNNs) as well as modules for time feature extractions to test spatial and motion indicators from video data. High-level preprocessing pipelines in combination with confidence scoring mechanism help make Synaptic Shield adaptive toward manipulation techniques such as FaceSwap and DeepFake. The accuracy of our model surpasses other deepfake detection models with a high accuracy of 98.3%. The above results are based on exhaustive experimentation on standard datasets like FaceForensics++, DeepFake detection challenge (DFDC), and Celeb DeepFake (Celeb-DF). Synaptic Shield is shown to be the best with outstanding results that maintain a higher confidence score equivalent to its precision and reliability. Scalability in having the capacity to accommodate various manipulation techniques and levels of video quality indicates robustness in offering an effective method toward ensuring integrity in digital media. The work is an important move forward in addressing the problems created by DeepFake technologies.
HDGC-hybrid task offloading framework using deep reinforcement learning and genetic algorithms for 6G edge cloud Radhakrishnan, Kaniezhil; Horng, Mong-Fong; Shankar Subramanian, Siva; Lo, Chun-Chih
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp236-247

Abstract

The rapid evolution of 6G networks has brought new challenges in the domain of task offloading (TO), particularly within edge computing environments that are heavily reliant on the internet of things (IoT). Traditional TO methods that based on rule-based heuristics or shallow learning techniques fail to adapt efficiently to the dynamic, unpredictable network conditions, resource heterogeneity, and varying task demands. The proliferation of edge computing, the IoT, and 6G networks has introduced new challenges in TO due to dynamic network conditions, resource heterogeneity, and unpredictable task demands. To address these challenges, this work proposes an innovative TO method that integrates deep reinforcement learning (DRL) with heuristic search methods. The combination of DRL and heuristic algorithms enhances adaptability, convergence speed, and decision-making efficiency, making it well-suited for real-time TO in complex and unpredictable environments This paper proposes a novel hybrid TO framework that integrates DRL with genetic algorithms (GA) to address these challenges. The proposed hybrid optimization technique offer promising solutions by leveraging the strengths of individual approaches to balance competing objectives, such as energy consumption, task completion time, and resource utilization. This method explores optimization strategies to enhance TO efficiency in decentralized environments mainly focusing on optimizing energy use while ensuring performance metrics like latency, throughput, and task deadlines are met.
FPGA implementation of high-performance Huffman encoder for image processing applications Ahmad Mahammad, Masood; Raju Uppala, Appala; Mazhar Hussain, Shaik; Marouthu, Anusha
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp68-77

Abstract

An optimized Huffman encoder is essential in all applications where it is necessary to achieve the best performance, such as audio coding, data encryption, data compression, and image processing applications. This article presents a space-optimized encoding scheme to maximize performance and minimize latency in Dual Huffman encoding. The proposed approach employs dynamic tree selection using Dual Huffman encoding. A Dual Huffman code with dynamic tree selection can be run in parallel to support high-throughput applications. The resulting design optimally creates the Huffman dual encoding. This codeword table is based on a dynamic tree generation and selection algorithm, leading to a faster encoding process with lower latency. The architecture was developed using Vivado Xilinx 2023.2 and tested on three different field programmable gate array (FPGA) platforms (Zynq 7045, Zynq 7100, and Kria KV260 AI Vision board). A performance comparison between devices demonstrates that the Kria KV260 had the lowest latency (100 ns), as opposed to the Zync 7045 and Zynq 7100, which had latencies of 200 ns and 150 ns, respectively. These results elucidate the scalability of the architecture and its suitability for real-time image compression. When implemented on the Kria KV260, the dynamic tree selection-based Dual Huffman encoder is capable of fast, parallel image compression. The compression makes it a good candidate for advanced FPGA-based image processing systems with internet of things (IoT) applications.
Advanced MRI-based deep learning for brain tumors: a five-year review of oncology–radiology–AI synergy Ramesh, Shrisha Maddur; Gururaj, Chitrapadi
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp214-223

Abstract

Rapid advancements in computer vision and machine learning have significantly revolutionized medical imaging one such application is brain tumor detection and classification. Deep learning has emerged as a powerful tool, which offers exceptional capabilities in handling complex medical datasets. However, the current systems still face challenges in achieving optimal accuracy, robustness and clinical interpretability. This study presents a comprehensive survey of brain tumor segmentation, classification and detection techniques using deep learning, metaheuristic and hybrid approaches. The detailed quantitative evaluations of conventional and emerging methods are conducted by examining key performance metrics, dataset characteristics, strengths, and limitations. This review highlights recent breakthroughs by analyzing state-of-the-art techniques from the past five years, research gaps and potential directions for future advancements. These findings provide insights into novel architectures, optimization strategies and clinical applications which ultimately guide researchers towards more robust, interpretable and clinically impactful artificial intelligence (AI)-driven solutions for brain tumor analysis.
Energy-efficient reconfigurable architectures for Edge AI in healthcare IoT: trends, challenges, and future directions Sutikno, Tole; Zakwan Jidin, Aiman; Handayani, Lina
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp1-20

Abstract

The integration of Edge artificial intelligence (AI) with internet of things (IoT) technologies is transforming healthcare applications, including wearable monitoring, telemedicine, and implantable medical devices, by enabling low-latency and intelligent data processing close to patients. However, stringent requirements on energy efficiency, reliability, real-time responsiveness, and data privacy continue to hinder scalable and long-term deployment in resource-constrained healthcare environments. Energy-efficient reconfigurable architectures—such as field-programmable gate arrays (FPGAs), coarse-grained reconfigurable arrays (CGRAs), and emerging memory-centric and heterogeneous platforms—have emerged as promising solutions to address these challenges by balancing flexibility, adaptability, and power efficiency. This review systematically examines recent advances in reconfigurable Edge AI architectures for healthcare IoT, highlighting key trends in hardware–software co-design, AI-assisted design automation, memory-centric optimization, and domain-specific overlays. It further identifies critical challenges, including energy–performance trade-offs, runtime reconfiguration overheads, security and privacy vulnerabilities, limited standardization, and reliability concerns in dynamic clinical settings. Finally, future research directions are outlined, emphasizing self-optimizing and context-aware architectures, secure and trustworthy reconfiguration mechanisms, unified frameworks for heterogeneous healthcare workloads, and sustainable, carbon-aware edge computing. Collectively, this review positions energy-efficient reconfigurable architectures as a foundational enabler for next-generation Edge AI in IoT-enabled healthcare systems.
FPGA implementation of a coprocessor architecture for random data generation and encryption Kumar, Manoj
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp21-30

Abstract

Coprocessors are designed to perform some specific tasks to enhance system performance and speed. Information security is the main focus in internet of thing (IoT), cryptography, and cybersecurity applications. In this work, a coprocessor architecture is designed to generate 4-bits of random data and perform encryption. Coprocessor architecture uses true random number generator (TRNG) and pseudo-random number generator (PRNG) architectures to generate random data. Modified linear feedback shift register (LFSR)-based PRNG and modified transition effect ring oscillator (TERO) and ring oscillator-based TRNG architectures are designed and implemented for performing encryption. A serial-in-parallel-out (SIPO) shift register circuit is used to generate 4-bit random data. A 15-bit instruction word is assigned to coprocessor architecture to perform its task. The coprocessor architecture is designed using VHSIC Hardware Description Language (VHDL) and implemented on an Artix-7 field programmable gate array (FPGA). All simulation and synthesis results of the proposed coprocessor architecture are obtained by the Xilinx Vivado 2015.2 tool. Coprocessor architecture efficiency (throughput (Mbps)/LUTs) is 2.31, and it operates at a 100 MHz clock.
Learning customer preference dynamics using rank-aware matrix factorization and enhanced collaborative filtering model Sundar, Sathya; Thevar Ramaraj, Eswara; Arumugam, Padmapriya
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp159-169

Abstract

Understanding how customer preferences evolve over time is a critical challenge for modern recommender systems operating in large-scale, implicit-feedback–driven e-commerce environments. The primary objective of this study is to develop a unified and interpretable framework that simultaneously models ranking-based preferences, collaborative similarity structures, and temporal behavioral evolution of customers. To achieve this, the study proposes a novel hybrid framework that integrates rank-aware matrix factorization (RA-MF), enhanced collaborative filtering (CF), K-means clustering, and temporal cluster migration matrices (TCMM) for learning customer preference dynamics. The ranking factorization model effectively captures implicit signals such as purchase frequency and recency decay, while CF provides complementary similarity-based insights. K-means segmentation reveals diverse customer personas, including high-value loyal buyers and exploratory shoppers, with significant differences in spending and purchasing behavior. Quantitative evaluations demonstrate strong performance improvements, with 11–18% gains in NDCG@10, 10–15% increases in Precision@10, and notable reductions in root mean square error (RMSE) and mean absolute error (MAE). The results highlight the framework’s ability to deliver both accurate recommendations and interpretable behavioral insights, offering valuable contributions to personalized marketing, customer retention, and data-driven e-commerce strategy.
Portable verification IP: a UVM-based approach for reusable verification environments in complex IP and SoC verification Chippagi, Harinagarjun; Sumalatha, Vangala
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp78-85

Abstract

Reusable and portable verification techniques are becoming more and more necessary due to the growing complexity of system-on-chip (SoC) designs and the need for quick time-to-market. In order to facilitate cross-project reusability, automation, and scalability in SoC verification, this paper introduces a portable verification IP (PVIP) framework based on the universal verification methodology (UVM). The suggested framework improves coverage efficiency and verification portability across heterogeneous platforms by integrating UVM with the portable stimulus standard (PSS). In comparison to traditional UVM-based methods, experimental evaluation shows that the PVIP framework achieves 92% functional coverage, enhances reusability by 87%, and shortens verification cycle time by 27%. These findings demonstrate how PVIP can greatly speed up verification closure, minimize engineering effort, and assist in the development of the next generation of intelligent, scalable, and industry-ready SoC verification environments.
Inquisitive biometric feature analysis and implementation for recognition tasks using camouflaged segmentation with AI and IoT Shankarrao Patil, Mahesh; J. Sarode, Harsha; Banubakode, Abhijit; Tukaram Patil, Prakash; Patil, Nutan; Varadarajan, Vijayakumar; Arrova Dewi, Deshinta
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i1.pp119-129

Abstract

A vital role in reconfigurable and embedded systems which are deployed in smart environements and healthcare monitoring applications is played by human activity recognition (HAR). However, the potential leakage of sensitive user attributes raises serious privacy issues due to collection of data from the end devices and it needs to be transmitted to more powerful platforms for inference. Addressing this key challenge is principally crucial for resource-constrained embedded systems where efficiency of energy is a chief design requirement. The aim of this paper is present an energy-aware, privacy-preserving HAR framework appropriate for low-power embedded platforms. A machine learning–based camouflaged signal segmentation technique is proposed to transform the data collected from the sensor by eliminating sensitive information while preserving activity-relevant features. For characterization of trade off between the energy consumption and accuracy of recognition, parameters are extensively tuned by careful optimization in this proposed model. Experimental evaluations demonstrate that the method significantly reduces the inference of sensitive attributes such as gender, age, height, and weight, with minimal impact on HAR accuracy. Furthermore, the system supports configurable trade-offs between energy usage and classification performance, making it suitable for implementation on low-power embedded devices.

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