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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 505 Documents
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A review of field-programmable gate array-based biomedical signal processing for public health applications Tole Sutikno; Aiman Zakwan Jidin; Lina Handayani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp320-338

Abstract

Biomedical signal processing is essential for modern diagnostics, monitoring, and preventive healthcare in public health and mobile health (mHealth) systems. Signals such as electroencephalography (EEG), electromyography (EMG), and heart rate variability (HRV) offer vital insights into brain, muscle, and cardiovascular health. However, achieving real-time, energy-efficient, and scalable processing remains challenging for conventional hardware such as central-processing units (CPUs), graphics-processing units (GPUs), and application-specific integrated circuits (ASICs). Field-programmable gate arrays (FPGAs) provide a promising alternative through their reconfigurability, parallelism, and adaptability to dynamic biomedical workloads. This review examines FPGA-based implementations for EEG, EMG, and HRV processing, focusing on key metrics including latency, throughput, and power efficiency. It also discusses design strategies such as low-power optimization, hardware–software co-design, and FPGA-based machine learning acceleration, with attention to data integrity and security in medical contexts. Integration with wearable, portable, and telemedicine platforms is explored, alongside comparative analyses with traditional computing architectures. The paper identifies challenges in power–performance trade-offs, design complexity, and clinical validation, and highlights emerging directions such as artificial intelligence (AI)-driven FPGA platforms, neuromorphic design, and sustainable low-cost solutions for large-scale health monitoring. Overall, FPGA-based biomedical signal processing emerges as a foundation for intelligent, efficient, and accessible next-generation public-health technologies.
AI-driven co-optimization of ONOFIC circuits and multiband antennas for low-power VLSI Ramavathu Ramesh Naik; Donapati Ramakrishna Reddy; Krishnanaik Vankdoth
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp306-319

Abstract

This paper presents an artificial intelligence (AI)-assisted optimization framework for on-off current feedback controlled (ONOFIC)-enhanced domino circuits implemented in advanced fin field-effect transistor (FinFET) and carbon nanotube field-effect transistor (CNTFET) technologies. The framework integrates artificial neural network (ANN) surrogate modeling with evolutionary optimization (genetic algorithm (GA), particle swarm optimization (PSO), and NSGA-II) to reduce leakage, improve energy efficiency, and enhance robustness under process voltage temperature (PVT) variations, aging effects (bias temperature instability (BTI)/hot carrier injection (HCI)), and antenna-induced parasitic coupling. By replacing repeated HSPICE simulations with fast ANN predictions, the proposed methodology reduces computational cost by more than 90% while achieving up to 30–35% gains in leakage and power-delay product (PDP)/energy-delay product (EDP) performance. The results demonstrate that ANN-assisted evolutionary optimization provides a scalable and technology-agnostic workflow suitable for next-generation internet of thing (IoT), radio frequency (RF)-integrated, and low-power very large scale integration (VLSI) platforms.
ESP-NOW based multi-node internet of things system for agricultural solar dryers with hybrid offline-online monitoring Rahmat Siswanto; Putri Dewintari; Sapar Sapar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp426-438

Abstract

Existing internet of things (IoT) systems for agricultural solar dryers rely on continuous internet connectivity, limiting deployment in remote rural areas with unreliable infrastructure. This study develops and validates a multi-node IoT architecture using ESP-NOW peer-to-peer communication that enables infrastructure-independent operation with optional ThingSpeak cloud synchronization. The system integrates ESP32 nodes, SHT41 sensors, relay-controlled actuators, and a hybrid solar-battery-grid power supply, deployed at a cocoa processing facility in South Sulawesi, Indonesia. Field evaluation confirmed: >95% packet delivery at 50 m, <10 ms latency, 94.3% cloud synchronization reliability, and 96% upload timing precision within ±2 s (σ=0.96 s). The dual-mode architecture sustained continuous local monitoring and actuator control during all network outages, with autonomous cloud reconnection requiring no manual intervention. Drying trials showed a -40 57% reduction in cocoa drying duration (3–4 days vs. 5–7 days baseline) through automated chamber control (40–60 °C; RH <60%). Energy analysis yielded an intensity of 0.12–0.17 kWh/kg dried output, with the IoT subsystem consuming less than 1% of total drying energy. The validated architecture provides a deployable, offline-capable, and energy-efficient solution for post-harvest monitoring in infrastructure-constrained environments, with applicability to diverse crop drying and storage scenarios.
High-performance approximate MAC multiplier using majority logic compressors for CNNs Selvarasan Radhakrishnan; Sudhagar Govindhaswamy; Rasadurai Kumaravel
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp269-280

Abstract

This research presents an optimized multiple accumulate (MAC) unit multiplier design for efficient convolutional neural network (CNN) operations. This design mainly focuses on making the multiplier systems smaller by using approximate majority compressor methods instead of the usual and traditional approximate methods. The traditional approximate multiplier compressor techniques are leads to increases in logic size, critical path delay, and power consumption; however, the proposed research mitigates these problems and solves them with a novelty-based approach in the Dadda multiplier technique. The novelty of this approach is to reduce the number of stages in the multiplier design using 4:2, 5:2, and 7:2 compressors. This compressor is designed with an approximate method using majority logic; compared to this traditional method, the proposed majority approximate compressor method processed less error differences in multiplication output. The proposed approaches resulted in significant reductions in area, power, and delay relative to traditional multipliers. This research compared seven unique comparisons of MAC-based multiplier architecture, and it will have been developed in Verilog hardware description language (HDL) and synthesized on the Xilinx Vertex-5 FPGA, providing reductions of 58.4% in lookup table (LUT) and 76.2% in occupied slices, and proving less power consumption. This design is a highly suitable approach for real-time CNN and digital signal processing (DSP) applications.
A real-time multi-modal deep learning framework for student attentiveness assessment in online learning environments Rajasekaran Mariswamy; P.V. Praveen Sundar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp450-460

Abstract

The rapid growth of online learning platforms has increased the need for intelligent systems capable of monitoring student attentiveness in real time to improve learning effectiveness and adaptive instruction. This paper proposes a multi-modal deep learning framework for attentiveness assessment by integrating visual, behavioral, and temporal information extracted from online classroom interactions. The proposed system consists of four major components, namely data acquisition, preprocessing and normalization, deep feature extraction with temporal learning, and attentiveness evaluation with analytics generation. Visual and spatial characteristics are learned using a convolutional neural network (CNN), while temporal behavioral patterns are captured through a long short-term memory (LSTM) network to model sequential engagement dynamics. The framework is designed to operate in both real-time and offline modes, enabling live monitoring during virtual classes as well as post-session analysis of recorded lectures. The computational pipeline is optimized through fixed-point processing, parallel convolution execution, and latency-aware temporal modeling, making it suitable for field programmable gate array (FPGA)-based and embedded implementations under constrained computational resources. Experimental evaluation conducted on an in-house dataset demonstrates that the proposed framework achieves 92.9% classification accuracy and a 91.9% F1-score, while maintaining strong generalization capability on cross-dataset benchmarks. Furthermore, latency analysis shows an average processing time of 31.6 ms per frame, enabling near real-time inference at approximately 30 frames per second.
Analysis of a compact wideband DGS-inspired octagonal patch antenna for sub-6 GHz 5G and IoT wireless systems Komalavalli Subramanian; Divya Subramani; Sornalatha Ravindran; Muthu Manickam Anbarasu; Mohan Chinnasamy; Anita Daniel
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp479-489

Abstract

The proposed compact wideband antenna is developed to meet the increasing demand for efficient and miniaturized radiators in sub-6 GHz fifth generation (5G) and internet of things (IoT) wireless systems. The design features an octagonal radiating patch integrated with modified H-shaped slots to enhance the current path and impedance matching, while a graded defected ground structure (DGS) is introduced to improve bandwidth (BW) and suppress unwanted surface wave effects. Fabricated on an FR4 substrate and energised by a simple stripline feed, the antenna maintains a compact size of 18×15 mm² without compromising performance. It achieves a wide fractional BW of 42.81% spanning 3.1–5.8 GHz, with a resonance centered at 4.6 GHz and obtained reflection coefficient of −36 dB, indicating excellent impedance matching. Additionally, the suggested antenna provides the maximum gain of 3.14 dB and an overall radiation efficiency of 80.5%, demonstrating stable radiation characteristics while making it ideal for small, low-profile 5G and IoT communication devices.
Predicting student academic outcomes from e-learning interaction data using hybrid machine learning models Sajithunisa Hussain; Jayachandran Jeyachidra
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp259-268

Abstract

The rapid growth of digital learning platforms has generated large volumes of student interaction data, providing opportunities for intelligent prediction of academic outcomes. Beyond educational analytics, such prediction tasks are relevant for reconfigurable systems, embedded platforms, very large scale integration (VLSI) accelerators, and internet of things (IoT)-enabled edge devices in smart learning environments. This study proposes a hybrid machine learning framework for predicting student performance using the e-learning student reactions dataset, which captures engagement patterns, behavioral responses, and interaction dynamics. Eight classifiers— eXtreme gradient boosting (XGBoost), K-nearest neighbors (KNN), decision tree (DT), random forest (RF), support vector machine (SVM), multilayer perceptron (MLP), radial basis function (RBF), and deep neural network (DNN)—are evaluated using both an 80–20 train–test split and K-fold cross-validation to assess accuracy and generalization. Results show the RBF model achieves the highest accuracy of 1.00, demonstrating its ability to capture complex, nonlinear behavior. From a systems perspective, the framework can be mapped onto field programmable gate arrays (FPGAs) or embedded devices, leveraging parallel computation for low-latency inference, and integrated with IoT-enabled smart classrooms for real-time edge analytics. These findings confirm that hybrid machine learning models not only improve student performance prediction but also serve as practical workloads for reconfigurable, embedded, and VLSI-based intelligent systems in digital education.
Revolutionizing night-time object detection in autonomous vehicles with SCL-YOLOv11 and ROA optimization Kondapalli Sri Vijaya; Gokula Krishnan Vasudevan; Pinagadi Venkateswara Rao; Therasa Michael; Balasubramanian Lalithambigai; Boddula Prathusha Laxmi
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp534-552

Abstract

Accurate object detection under low-light conditions is a critical requirement for reliable perception in autonomous driving systems. However, night-time environments often suffer from poor illumination, noise, and reduced feature visibility, which significantly degrade the performance of conventional object detection models. To address this challenge, this paper proposes spatial contrast learning (SCL)-you only look once version 11 (YOLOv11), an enhanced object detection framework designed for night-time scenarios. The proposed approach integrates SCL to improve feature discrimination in dark regions and employs the revolution optimization algorithm (ROA) for effective model parameter optimization. The framework is evaluated on three benchmark night-time datasets, ExDark, LLVIP, and BDD100K, to assess its detection performance. Experimental results demonstrate that the proposed model achieves a mAP@50 of 72.9%, improving the baseline YOLOv11 by 9.5% while also reducing inference latency by 18.3%. Comparative evaluations with existing detectors further confirm that the proposed method provides improved accuracy and efficiency for night-time object detection. These results indicate that the proposed framework can enhance perception reliability for autonomous driving applications operating in low-light environments.
Graph neural network-based biomedical misinformation detection with semantic consistency analysis Siva Dhievaraj; Agusthiyar Ramu
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp439-449

Abstract

Conventional misinformation detection approaches primarily rely on textual features and deep learning (DL) classifiers, which often fail to capture complex relationships among biomedical entities and the underlying scientific context of health claims. To address this limitation, this study proposes a graph neural network (GNN)-based biomedical misinformation detection framework that integrates knowledge graph propagation with semantic consistency verification. Initially, key biomedical entities such as diseases, treatments, and biological processes are extracted and mapped into a structured biomedical knowledge graph (BKG) to represent semantic relationships. A graph attention network (GAT) is then employed to model relational dependencies and propagate contextual information across connected entities, enabling the detection of hidden inconsistencies in biomedical claims. The proposed model is evaluated using benchmark biomedical misinformation datasets, including Reliable COVID-19 News Dataset, 2021 (ReCOVery), COVID-19 Healthcare Misinformation Dataset, 2020 (CoAID), and 2018–2020 biomedical health news corpus (HealthStory). Experimental results demonstrate that the proposed framework achieves an average detection accuracy of 96.3%, outperforming conventional long short-term memory (LSTM), convolutional neural networks (CNN), and transformer-based models in terms of precision, recall, and F1-score. The findings highlight that integrating structured biomedical knowledge with graph-based reasoning significantly enhances the reliability and interpretability of misinformation detection systems.
Matter protocol-enabled device onboarding for cross-platform internet of things systems Geetishree Mishra; Hemavathi Hemavathi; Harish V Mekali
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 15, No 2: July 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v15.i2.pp406-415

Abstract

The Matter protocol, created by the connectivity standards alliance (CSA), comes in with a single standard to make sure these devices can connect and be controlled across platforms like Google Home, Apple HomeKit, Amazon Alexa, and Samsung SmartThings. The rapid expansion of the internet of things (IoT) is driving the urgent need for secure and efficient onboarding processes for a wide range of connected devices. It necessitates a robust framework to seamlessly integrate new additions into existing systems while upholding security standards. This initiative focuses on implementing the Matter protocol on ESP32 devices, employing a Raspberry Pi hub as the central communication point to facilitate smooth device-to-hub interactions. This work presents the onboarding devices for interconnected IoT systems using the Matter protocol. The Matter device is configured and tested within the Amazon ecosystem using an Alexa Echo Dot, as well as with the smart home assistant ecosystem along with a smartphone application. By configuring the Raspberry Pi hub as a designated Matter hub and exploring interactions within the home assistant ecosystem supporting diverse platforms like Apple HomeKit and Google Home, the work enhanced interoperability and broadened the utility of IoT devices within an interconnected network. This initiative forges a foundation for an adaptable and cohesive IoT environment.

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