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INDONESIA
Indonesian Journal of Electrical Engineering and Computer Science
Published by Institute of Advanced Engineering and Science
ISSN : 25024752     EISSN : 25024760     DOI : -
Core Subject :
Arjuna Subject : -
Articles 57 Documents
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Search results for , issue "Vol 13, No 2: February 2019" : 57 Documents clear
Frequency tuning varactor-loaded reconfigurable antenna for m-WiMAX and WLAN applications S. M. Shah; K. Hamdan; Z. Z. Abidin; F. C. Seman; S. A. Hamzah; N. Katiran; F. Zubir
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp779-786

Abstract

A design approach for a microstrip patch antenna to achieve the reconfigurable dual-band operation with a tunable device is presented in this work. The approach uses a BB833 varactor diode in the middle of a slotted patch antenna which which is able to produce dual-band resonant frequencies. The reconfigurable antenna is designed and simulated in CST Microwave Studio® software and is later, fabricated on a FR-4 substrate with a dielectric constant,  of 4.5, loss tangent, tan δ of 0.019 and thickness, h of 1.6 mm. By changing the DC voltages of the varactor diode, different capacitance values of the varactor diode are obtained which dictate the specific resonant frequencies. From the simulation results, the capacitance value of 0.5 pF with a bias voltage of 2.0 V is chosen as it produces the required dual-band resonant frequencies at 3.38 GHz and 5.37 GHz for desired applications in the m-WiMAX and WLAN bands.
Feature analysis for stage identification of Plasmodium vivax based on digital microscopic image Hanung Adi Nugroho; I Md. Dendi Maysanjaya; Noor Akhmad Setiawan; E. Elsa Herdiana Murhandarwati; Widhia K.Z Oktoeberza
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp721-728

Abstract

Plasmodium parasite is identified to confirm malaria disease.  Paramedics need to observe the presence of this parasite prepared on thick and thin blood films under microscope.  However, false identification still occurs which is caused by human factor during the examination.  Thus, malaria identification based on digital image processing has been widely developed to overcome the error possibility.  This paper proposes a scheme to identify and classify the stages of Plasmodium vivax parasite on digital microscopic image of thin blood films based on feature analysis.  Shape and texture features are extracted from segmented parasite objects.   Feature selection based on wrapper method is then conducted to obtain relevant features which may contribute in improving the classification result.  The classification process is conducted based on Naïve Bayes classifier.  The performance of proposed method is evaluated using 73 digital microscopic images of P.vivax parasite on thin blood films comprising of 29 trophozoites, 10 schizonts and 34 gametocytes stages.  By using six selected features including perimeter, dispersion, mean of intensity, ASM, contrast GLCM and entropy GLCM, the proposed scheme achieves the best classification rate with the accuracy, sensitivity and specificity of 97.29%, 97.30% and 97.30%, respectively.  This indicates that the proposed scheme has a potential to be implemented in the development of a computerised aided malaria diagnosis system for assisting the paramedics.
User selection protocol in DF cooperative networks with hybrid TSR-PSR protocol based full-duplex energy harvesting over rayleigh fading channel: system performance analysis Phu Tran Tin; Le Anh Vu; Tan N. Nguyen; Thanh-Long Nguyen
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp534-542

Abstract

Cooperative communication has been recently proposed in wireless communication systems for exploring the inherent spatial diversity in relay channels. In this work, we investigate the system performance of the energy harvesting full-duplex (FD) decode-and-forward (DF) hybrid time switching-power splitting relaying TSR-PSR (TPSR) protocol relaying network. In the selection scheme, the best user selection protocol is proposed and investigated. Mainly we derive the closed-form expression for the outage probability, system throughput and the symbol error rate (SER) of the system. Numerical results are also presented by the Monte Carlo simulation to validate the theoretical analysis in connection with the all possible parameters in the comparison between TSPR, TSR and PSR cases. The research results show that TPSR case is better than the others in term of outage probability and SER.
Implementation of an ARM-based system using a Xilinx ZYNQ SoC Omar Salem Baans; Asral Bahari Jambek
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp485-491

Abstract

ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.
A noble approach to develop dynamically scalable namenode in hadoop distributed file system using secondary storage Tumpa Rani Shaha; Md. Nasim Akhtar; Fatema Tuj Johora; Md. Zakir Hossain; Mostafijur Rahman; R. B. Ahmad
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp729-736

Abstract

For scalable data storage, Hadoop is widely used nowadays. It provides a distributed file system that stores data on the compute nodes. Basically, it represents a master/slave architecture that consists of a NameNode and copious Data Nodes. Data Nodes contain application data and metadata of application data resides in the Main Memory of NameNode. In cached approach, they fragment the metadata depending on the last access time and move the least frequently used data to secondary memory. If the requested data is not found in main memory then the secondary data will be loaded again on the RAM. So when the secondary data reloads to the primary memory then the NameNode main memory limitation arises again. The focus of this research is to reduce the namespace problem of main memory and to make the system dynamically scalable. A new Metadata Fragmentation Algorithm is proposed that separates the metadata list of NameNode dynamically. The NameNode creates Secondary Memory File in perspective of the threshold value and allocates secondary memory location based on the requirement. According to the proposed algorithm the maximum third, out of fourth of main memory is used at the secondary file caching time. The free space aids in faster operation by Dynamically Scalable NameNode approach. This proposed algorithm shows that the space utilization is increased to 17% and time utilization is increased to 0.0005% with the comparison of the existing fragmentation algorithm.
A comparison of performance between double-gate and gate-all-around nanowire MOSFET Nor Fareza Kosmani; Fatimah A.Hamid; M. Anas Razali
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp801-807

Abstract

Due to the rapid scaling of Complementary Metal-Oxide-Semiconductor (CMOS), the structure of the planar MOSFET approaches the scaling limits when the short channel effects (SCEs) become the main problem. The Double-Gate and Gate-all-Around nanowire MOSFETs are said to be the promising candidate to replace the planar MOSFET in order to pursue CMOS scaling. Therefore, this paper present the result of device simulation using Silvaco TCAD tools for Double-Gate and Gate-All-Around nanowire MOSFETs. The purpose of this simulation work is to compare the performance of GAA nanowire and DG MOSFET and then study the effect of physical parameter on electrical behavior for both devices. The result of the simulated model of Gate-All-Around nanowire is compared with published data.  It was found that when the gate length of DG was scaled from 80nm to 10nm, the subthreshold slope is increasing from 62mV/dec to 162.7mV/dec. While for GAA, the subthreshold slope is increasing from 65.8mV/dec to 127mV/dec. The threshold voltage in DG and GAA at Lg=80nm are 0.40646V and -0.17505V respectively. Even though heavy doping was good for suppressing SCE, the lower doping concentration is desirable as the DG and GAA nanowire had higher on-state currents with 1.42x10-3Aand 3.23x10-4A respectively. It also showed that the threshold voltage of DG and GAA nanowire increase from -0.0734V to 0.2312V and -0.0319V to 0.2232V respectively when the channel doping is varies from lower to higher concentration.
Low latency and energy efficient cluster based routing design for wireless sensor network Basavaraj G.N; Jaidhar C.D
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp615-625

Abstract

Wireless sensor network (WSN) has attained wide adoption across various sectors and is considered to be key component of future real-time application such as BigData, Internet of things (IoT) etc. The modern application requires low latency and scalable real-time data access considering heterogeneous network. However, provisioning low latency real-time data access incurs energy overhead among sensor device. Clustering technique aided in providing scalability and minimizing energy consumption among sensor device. However, it incurs energy overhead among cluster head and sensor device closer to sink. To address, many optimization technique is been presented in recent time for optimal cluster selection. However, these technique are designed considering homogenous network. To address, this work presented low latency and energy efficient routing (LLEER) design for heterogeneous WSN. The LLEER adopts multi-objective function such asconnectivity, connection time, radio signal strength, coverage time, and network traffic for cluster head and hop node selection. Experiment are conducted to evaluate LLEER design shows significant performance improvement over state-of-art model in terms of network lifetime considering total node death, first node death, and loss of connectivity, communication overhead, and packet transmission latency. Proposed LLEER brings a good trade-off between energy efficiency, and latency requirement of future real-time application.  
Evolution of H-shaped dielectric resonator antenna for 5G applications S. Z. N. Zool Ambia; M. H. Jamaluddin; M.R. Kamarudin; J. Nasir; R.R. Selvaraju
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp562-568

Abstract

In this paper, an H-shaped Dielectric Resonator Antenna (DRA) with a Microstrip Slot Aperture (MSA) is presented and investigated at 26 GHz. In order to widen the bandwidth operation, the slot aperture feeding technique is applied. The designed DRA with relative permittivity, εr of 10 is mounted on a Duroid substrate with a relative permittivity, εr of 2.2, loss tangent of 0.0009 and a thickness of 0.254mm. The proposed antenna with overall size of 20 x 20 x 5.27 mm3 achieves good impedance matching, gain of 7.61 dB and good radiation patterns. An impedance bandwidth of 21.44%, covering the frequency range from 24.72 GHz to 30.62 GHz made the antenna has potential for millimeter wave and 5G applications.
Performance enhancement of OCDMA system based on sequential algorithm (SeQ) Code C. A. S. Fazlina; C. B. M. Rashidi; S. N. Azemi; S. A. Aljunid; S. Yaakob
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp831-836

Abstract

This paper presents a new class of Sequential Algorithm (SeQ) code for Optical Code Division Multiple Access (OCDMA) system. The SeQ code has advantages of various cross – correlation property at any given number of users, and code weights. The result shown, at error floor BER = 10-09, the SeQ code capability to support 190 numbers of simultaneous users was higher than those achieved by FCC (W=4), DCS (W=4) and MFH (W=4). SeQ code excellently support 190 number of users due to due to the arrangement of code algorithm and flexibility cross-correlation (0 and 1) role. In addition, SeQ code capable to support up to 70 km for bit rate 155 Mbps in comparison 622 Mbps, 1 Gbps, and 2 Gbps be able to support 40km, 30km and 20km respectively. Hence, we can ascertain that PIIN and MAI are successfully eliminated for SAC-OCDMA coding system.
An angle speed and thrust relationship of the rotor system in the quadcopter aircraft Al Al; Arfita Yuana Dewi; Antonov Bachtiar; Dwi Harinita
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 2: February 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i2.pp469-474

Abstract

Utilizing Quadcopter were still many obstacles such as; plane easy to fall; the battery is not durable; vulnerable to weather conditions and others. The research and development has grown to improve aircraft facilities and capabilities. Many parameters related to aircraft lift capability factors; fly long; flying high; type of motor; the type of propeller: including the sensors and control systems used. This study was to find the relationship between changes in the BLDC motor voltage source to the rotor angle velocity (ω); rotor speed to rotor lift (Ft);  wind speed to rotor lift; push the following rotor (Ct). Empirical testing was conducted in the laboratory to find the relationship of these parameters. The results data show that; the lift power generated with rotational speed was not proportional, non linearity occurs when the rotor was released from the self and starts pulling the strain gauge when the rotation speed reaches around 65 rps. Once the rotation speed of the rotor is able to reach up to 1.5 Newton lift then the thrust rising trend sharply increasing toincreasing of the rotor speed. A motor hade 1200 KV and blade with a radius of 0.12 m, then obtained thrust (Ct) of 1.732.

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