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Computer Architecture and Signal Processing
Published by Asosiasi Pengelola Jurnal Informatika dan Komputer Indonesia
ISSN : -     EISSN : 31240003     DOI : 10.66472
Core Subject :
Aims This journal aims to disseminate research on computer architecture and digital signal processing as the foundation for high-performance, embedded, and intelligent computing systems. Scope Computer architecture and organization Embedded systems and IoT hardware Digital signal processing techniques Microprocessor and microcontroller systems Hardware–software co-design Communication and multimedia signal processing Energy-efficient and high-performance computing architectures
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Articles 7 Documents
 1 
Memory Hierarchy Optimization and Cache Aware Signal Processing Pipelines for Next Generation High Throughput Computing Architectures Hari Imbrani; Achmad Subagdja
Computer Architecture and Signal Processing Vol. 1 No. 1 (2026): March: Computer Architecture and Signal Processing
Publisher : Asosiasi Pengelola Jurnal Informatika dan Komputer Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.66472/casp.v1i1.32

Abstract

This research explores the impact of Cache Aware optimizations on signal processing pipelines in High Throughput computing systems. The growing demand for efficient memory management in modern computing systems, especially for data-intensive applications such as artificial intelligence (AI) and multimedia processing, necessitates the development of optimized memory hierarchies. Traditional memory systems often suffer from memory bottlenecks, significantly reducing the performance of these systems. This study investigates how memory hierarchy optimizations, particularly cache line aware optimization, dependency-aware caching, and adaptive cache replacement algorithms, can mitigate these challenges and improve system performance. Through analytical modeling and experimental benchmarking, this work evaluates various memory hierarchy configurations, including processing-in-memory (PIM) and three-dimensional integrated circuits (3D ICs), comparing them to conventional systems. The results demonstrate that Cache Aware optimizations lead to a reduction in memory access latency by up to 30%, while throughput improved by up to 40%. Additionally, cache hit rates increased by 25%, and energy consumption was reduced by up to 20%, highlighting the effectiveness of optimized memory management. The research contributes to the field by providing valuable insights into the design and implementation of efficient signal processing pipelines. It also identifies key challenges, including the need for dynamic occupancy mechanisms and DAG-aware scheduling algorithms, and suggests potential areas for future research, such as the exploration of collaborative caching approaches and further optimization of cache-adaptive algorithms. This work lays the foundation for more efficient, high-performance computing systems that can handle large datasets and complex tasks in real-time applications.
Low Power Microcontroller Based System Design Employing Efficient DSP Algorithms for Smart Cyber Physical Embedded Monitoring Hayadi Hamuda; Novia Permata Atmadja; Rahmadi Asri
Computer Architecture and Signal Processing Vol. 1 No. 1 (2026): March: Computer Architecture and Signal Processing
Publisher : Asosiasi Pengelola Jurnal Informatika dan Komputer Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.66472/casp.v1i1.33

Abstract

The integration of Digital Signal Processing (DSP) algorithms in low power microcontroller based embedded systems has emerged as a promising solution to optimize energy efficiency without compromising signal accuracy and performance. This study focuses on the design and optimization of DSP algorithms specifically for microcontrollers, aimed at achieving real-time, reliable monitoring for applications such as healthcare, environmental sensing, and IoT devices. The research highlights the system's ability to handle complex signal processing tasks while maintaining low power consumption, ensuring long-term, continuous operation in remote or battery-powered environments. The system employs various techniques, including advanced power management strategies such as dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS), along with lightweight AI algorithms and model pruning, to minimize energy use. The results show significant reductions in power consumption compared to traditional systems, particularly during continuous monitoring tasks. Despite this, the optimized DSP algorithms maintain or even enhance signal accuracy, ensuring that critical monitoring data remains reliable. Furthermore, the system demonstrates robust performance and reliability over extended periods, making it suitable for long-term deployment in critical applications such as wearable medical devices and industrial sensors. This research provides a foundation for the development of future low power embedded systems, emphasizing the importance of DSP-aware optimization in achieving energy-efficient and high-performance monitoring. Future improvements may include advanced AI-driven power optimization techniques, enhanced scalability, and cross-domain interoperability, ensuring that these systems can be effectively deployed across diverse applications, from healthcare to environmental monitoring.
High Performance Communication Protocols Integrated with Adaptive Signal Processing Engines for Scalable Multi Core Architectures Lukman Medriavin Silalahi; Mia Galina; Antonius Suhartomo
Computer Architecture and Signal Processing Vol. 1 No. 1 (2026): March: Computer Architecture and Signal Processing
Publisher : Asosiasi Pengelola Jurnal Informatika dan Komputer Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.66472/casp.v1i1.34

Abstract

This study investigates the integration of high performance communication protocols with adaptive signal processing engines in multi-core systems, aiming to enhance scalability, throughput, and inter-core communication efficiency. The challenges inherent in traditional multi core architectures, such as communication overhead, latency, and scalability limitations, are addressed through the incorporation of Network-on-Chip (NoC) architectures and adaptive signal processing techniques. By using a multi-core digital signal processing (DSP) platform, the study evaluates the performance improvements achieved by this integration under varying workloads and core configurations. The experimental results show a 35% improvement in throughput and a 25% reduction in communication latency, highlighting the effectiveness of adaptive communication protocols in managing data traffic between cores and reducing bottlenecks. The integration of NoC architecture facilitates parallel data transfers, while adaptive signal processing engines ensure that data flows more efficiently across the cores, enhancing system responsiveness, especially under high data rate conditions. Furthermore, the study explores the scalability of the proposed system, demonstrating its ability to maintain high performance as core counts increase. The findings emphasize the potential of combining advanced communication protocols with adaptive signal processing for optimizing multi-core system performance. Practical implications of this research include the design of scalable, flexible, and efficient multi core architectures suitable for complex, data-intensive applications. Future research should focus on further refining communication protocols and exploring additional integration strategies to enhance the adaptability and scalability of multi-core systems in next-generation computing environments.
Hardware Software Co Design of Deep Learning Accelerated Digital Signal Processing Cores for Low Latency Multimedia Applications Taufiq Dwi Cahyono; Abdul Muchlis; Sandy Suryady
Computer Architecture and Signal Processing Vol. 1 No. 1 (2026): March: Computer Architecture and Signal Processing
Publisher : Asosiasi Pengelola Jurnal Informatika dan Komputer Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.66472/casp.v1i1.36

Abstract

The increasing demand for low latency and high-throughput multimedia applications has spurred significant advancements in hardware software co design. This study explores the integration of custom digital signal processing (DSP) hardware accelerators with optimized software frameworks to enhance deep learning accelerated DSP tasks. The proposed co design approach significantly reduces latency and improves throughput compared to traditional software-only DSP implementations. Through the development of custom hardware accelerators built with FPGA technology, the system achieves up to a 1.85x reduction in latency and a 1.5x improvement in throughput for real-time multimedia tasks such as image recognition, video decoding, and audio processing. The combination of hardware and software optimizations allows for better resource utilization, enabling the parallel processing of computationally intensive tasks while the software framework handles less demanding operations. Additionally, the co design system demonstrated improved energy efficiency, making it highly suitable for embedded systems. The results show that the hardware software co design approach offers substantial advantages in performance, latency reduction, and energy efficiency, positioning it as a viable solution for real-time multimedia applications. The findings have important implications for applications requiring fast data processing, such as autonomous driving, healthcare, and disaster management. Future research could explore alternative hardware accelerators, advanced software optimizations, and AI-based resource management to further improve the system’s efficiency and scalability for more complex multimedia tasks.
Design and Performance Evaluation of Energy Efficient Heterogeneous Microprocessor Architectures for Real Time Signal Processing in Edge IoT Systems Dani Sasmoko; Widya Aryani; Dwi Atmodjo WP
Computer Architecture and Signal Processing Vol. 1 No. 1 (2026): March: Computer Architecture and Signal Processing
Publisher : Asosiasi Pengelola Jurnal Informatika dan Komputer Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.66472/casp.v1i1.37

Abstract

Edge-Internet of Things (Edge IoT) systems are increasingly integral to applications that require real time signal processing, particularly where low latency and energy efficiency are critical. This paper explores the design and performance evaluation of a heterogeneous microprocessor architecture aimed at optimizing energy consumption and real time performance. The heterogeneous architecture integrates multiple types of cores, such as Central Processing Units (CPUs), Digital Signal Processors (DSPs), and Graphics Processing Units (GPUs), to allocate tasks based on computational demand. The proposed design significantly reduces energy consumption, particularly during high-performance tasks, while maintaining real time processing guarantees. Simulation-based performance evaluation was conducted to assess the energy efficiency, latency, and overall system performance under varying workloads, including real time Digital Signal Processing (DSP) benchmarks. The results showed that the heterogeneous architecture outperformed traditional homogeneous processors, demonstrating up to a 19-fold improvement in energy efficiency. Furthermore, the system reduced latency by up to 45% in real time applications, making it particularly suitable for Edge IoT environments such as industrial automation and smart healthcare, where both performance and energy efficiency are critical. Despite some trade-offs in task scheduling complexity, the heterogeneous design was able to balance power consumption and computational performance effectively. The findings suggest that this architecture can serve as a foundation for future Edge IoT systems, providing significant advantages in terms of energy efficiency, real time processing, and scalability. Future work will focus on further optimization of the architecture and exploring its application across various IoT environments.
Data-Driven Learning Analytics Conceptual Framework for Automated Competency Mapping in Outcome-Based Education: A Design Science Research Approach Hasbu Naim Syaddad; Zainal Arifin Hasibuan; Bobi Kurniawan S; Sri Supatmi; Agus Nursikuwagus; Citra Noviyasari
Computer Architecture and Signal Processing Vol. 1 No. 2 (2026): June: Computer Architecture and Signal Processing
Publisher : Asosiasi Pengelola Jurnal Informatika dan Komputer Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.66472/casp.v1i2.396

Abstract

The implementation of Outcome-Based Education (OBE) in higher education demands precise measurement of Graduate Learning Outcomes (CPL) and Course Learning Outcomes (CPMK). However, current conventional Learning Management Systems (LMS) remain static and centered on final performance metrics (grades), thus failing to map student academic profiles into sub-competencies in a real-time and granular manner. This study proposes a conceptual artifact in the form of an Intelligent Tutoring System (ITS) architecture based on Learning Analytics (LA) and Knowledge Graphs to automate competency mapping. Through the Design Science Research Methodology (DSRM) approach, this framework designs a data fusion pipeline that integrates high-resolution academic log data with curriculum ontologies. The proposed architecture consists of three main layers: data acquisition, predictive modeling using Machine Learning, and a recommendation engine based on Explainable AI (XAI). This conceptual framework provides a blueprint for higher education institutions to transform from reactive curriculum evaluation into precise and auditable adaptive learning governance.
Adaptive-Cognitive Smart Farming Architectures for Food Security Resilience: A Systematic Literature Review of IoT and AI-Based Approaches Ridho Taufiq Subagio; Zainal Arifin Hasibuan; Bobby Kurniawan; Sri Supatmi; Hidayat Hidayat; Citra Noviyasari
Computer Architecture and Signal Processing Vol. 1 No. 2 (2026): June: Computer Architecture and Signal Processing
Publisher : Asosiasi Pengelola Jurnal Informatika dan Komputer Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.66472/casp.v1i2.445

Abstract

Food security resilience has become an increasingly critical global concern due to the combined effects of climate change, population growth, and resource scarcity. Conventional agricultural practices are no longer sufficient to meet rising food demands, thereby necessitating the adoption of intelligent and adaptive technological solutions. Smart farming, enabled by the integration of the Internet of Things (IoT) and Artificial Intelligence (AI), has emerged as a promising approach to enhance agricultural productivity, efficiency, and sustainability. However, existing smart farming systems remain fragmented and lack adaptive and cognitive capabilities required to dynamically respond to environmental variability. This study proposes an adaptive-cognitive smart farming architecture that integrates IoT, AI, edge-fog-cloud computing, federated learning, and digital twin technologies into a unified framework. A Systematic Literature Review (SLR) is conducted to synthesize insights from 60 high-quality publications indexed in IEEE, Elsevier, and Scopus databases. The proposed architecture adopts a multi-layered design consisting of sensing, edge-fog, cloud, cognitive, and application layers, enabling real-time data processing, distributed intelligence, and adaptive decision-making. To validate the proposed model, experimental simulations are performed using key performance indicators, including accuracy, mean squared error (MSE), latency, and resource efficiency. The results indicate that the proposed approach achieves superior performance, with an accuracy of 89%, a substantial reduction in latency, and improved resource utilization. These findings demonstrate that incorporating adaptive and cognitive intelligence significantly enhances system responsiveness and decision-making capabilities. This study contributes to both theory and practice by introducing a comprehensive framework for next-generation smart farming systems, ultimately supporting food security resilience in an increasingly uncertain environment.

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