Claim Missing Document
Check
Articles

Found 6 Documents
Search

Enhancing Multilevel Inverter Performance: A Novel Dung Beetle Optimizer-based Selective Harmonic Elimination Approach Taha, Taha A.; Neamah, Muthanna Ibrahim; Ahmed, Saadaldeen Rashid; Taha, Faris Hassan; Bektaş, Yasin; Desa, Hazry; Yassin, Khalil Farhan; Ibrahim, Marwa; Hashim, Abdulghafor Mohammed
Journal of Robotics and Control (JRC) Vol 5, No 4 (2024)
Publisher : Universitas Muhammadiyah Yogyakarta

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.18196/jrc.v5i4.21722

Abstract

This paper introduces a novel approach for enhancing the performance of multilevel inverters by applying a dung beetle optimizer (DBO)-based Selective Harmonic Elimination (SHE) technique. Focusing on a 3-phase multilevel inverter (MLI) with a non-H-bridge structure, the proposed method offers advantages such as cost-effective hardware implementation and eliminating the traditional H-bridge inverter requirement. To assess its efficacy, we compare the presented DBO-based SHE technique (DBOSHE) with Genetic Algorithm (GA) and Particle Swarm Optimization (PSO), evaluating their ability to determine optimal switching angles for achieving low-distorted load voltage. Unlike methods reliant on time-consuming calculations or fixed solutions, DBO provides a flexible approach, considering multiple possibilities to yield accurate switching angles. Using Simulink, harmonic component values and Total Harmonic Distortion (THD) are obtained for each optimization technique, specifically emphasizing on 9-level and 11-level MLI topologies. Our study aims to identify the most effective optimization technique for achieving lower THD and THDe values while eliminating odd-order harmonics from the 3-phase load voltage. Finally, we demonstrate the effectiveness of employing DBO for THD and THDe optimization within the SHE technique.
Real-Time Optimal Switching Angle Scheme for a Cascaded H-Bridge Inverter using Bonobo Optimizer Taha, Taha A.; Wahab, Noor Izzri Abdul; Hassan, Mohd Khair; Zaynal, Hussein I.; Taha, Faris Hassan; Hashim, Abdulghafor Mohammed
Journal of Robotics and Control (JRC) Vol 5, No 4 (2024)
Publisher : Universitas Muhammadiyah Yogyakarta

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.18196/jrc.v5i4.21701

Abstract

This study demonstrates a novel method for using the Bonobo Optimizer (BO) to selective harmonic elimination in a cascaded H-Bridge Multilevel Inverter (CHB-MLI) running on solar power. The primary objective is to calculate, in real time, the optimal switching angles for eliminating low-order harmonics while maintaining a constant output voltage despite variations in the input voltage. To prove that the BO algorithm works, tests were done on a three-phase, seven-level CHB-MLI that compared it to other evolutionary algorithms like the genetic algorithm (GA) and particle Swarm optimization (PSO). An adaptive BO-Artificial neural network (BO-ANN) based system was developed to compute real-time switching angles and applied to a 7-level CHB-MLI. The results demonstrate that the BO algorithm is the most accurate and fastest evolutionary algorithm for calculating optimal switching angles. This study illustrates the BO algorithm's effective utilization in real-time harmonic elimination applications in CHB-MLI.
Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling Abdul-Kadir, Firas Natheer; Hashim, Yasir; Shakib, Muhammad Nazmus; Taha, Faris Hassan
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 1: February 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i1.pp780-787

Abstract

This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.
Designing an optimal PID controller for a PV-connected Zeta converter using genetic algorithm Hussain, Abadal-Salam T.; Taha, Faris Hassan; Fadhil, Hilal A.; Salih, Sinan Q.; Taha, Taha A.
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 15, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v15.i1.pp566-576

Abstract

This paper suggests a way of fixing problems of voltage fluctuations and peak overshoot in a PV-connected Zeta converter system. The Zeta converter in the proposed approach is controlled using proportional integral derivative (PID) while a genetic algorithm (GA) calculates the PID coefficients based on the control mechanism. The performance of the designed system was analyzed in a MATLAB/Simulink environment. The analysis showed that the proposed system reduced the output voltage ripple and peak overshoot during transient conditions by providing feedback to the converter through the PID controller, this is a significant improvement when compared to the results found without a PID controller.
Definite time over-current protection on transmission line using MATLAB/Simulink Taha, Taha A.; Zaynal, Hussein I.; T. Hussain, Abadal-Salam; Desa, Hazry; Taha, Faris Hassan
Bulletin of Electrical Engineering and Informatics Vol 13, No 2: April 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v13i2.5301

Abstract

This paper has investigated the application of the definite time over-current (DTOC) which reacts to protect the breaker from damage during the occurrence of over-current in the transmission lines. After a distance relay, this kind of over-current relay is utilized as backup protection. The overcurrent relay will provide a signal after a predetermined amount of time delay, and the breaker will trip if the distance relay does not detect a line failure. As a result, this over-current relay functions with a time delay that is just slightly longer than the combined working times of the distance relay and the breaker. This DTOC is tested for various types of faults which are 3- phase fault occurring at load 1, 3-phase fault occurring at load 2, a 3-phase fault occurring before primary protection, and the behaviour of voltage and current with a failed primary protection. All the results will be obtained using the MATLAB/Simulink software package.
Investigation and Design of High Efficiency Quadrature Power Amplifier for 5G Applications Taha, Faris Hassan; Hussein, Shamil H.; Yaseen, Mohammed T.; Fadhil, Hilal A.; Assi, Saad A.; Desa, Hazry; Imran, Ahmed Imad; Radhi, Ahmed Dheyaa; Almulaisi, Taha
International Journal of Robotics and Control Systems Vol 5, No 2 (2025)
Publisher : Association for Scientific Computing Electronics and Engineering (ASCEE)

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.31763/ijrcs.v5i2.1881

Abstract

The rapid rise of the high data rate requirements in modern wireless communications, which include Wi-Fi, LTE, and 5G, demands that appropriate linear and efficient transmitter architecture gets designed. The increased power amplifier (PA) efficiency in the output power back-off (OPBO) is one of the major challenges because it is difficult to achieve PA power efficiency and linearity at the same time. The current study provides design and simulation of a Quadrature Power Amplifier (QPA) for application in 5G in the 5.8 GHz band using 120nm CMOS technology. The proposed QPA system combines Envelope Elimination and Restoration (EER) technique with direct I and Q signal modulation, quite a different solution from the “conventional” approaches of EER and represents very a bandwidth efficient one. Hard-switching drivers as well as the optimized matching networks are used by the system to ensure that there is high power transfer capability and low distortion. In the design process the source impedance is optimized using a source pull simulation and the load impedance is optimized by using a load pull simulation; then, the L-type network is designed to realize optimal matching. For use in implementation, the Rogers RO-5880 material is applied using transmission lines set up through the microstrip techniques in a bid to reduce the losses and parasitic ones. Simulation results show that the QPA obtains a peak output power of 24.35dBm and a power-added efficiency (PAE) of 70% at 5.8 GHz. The best input and output impedances were:  and , respectively. In addition, the envelope and transient simulations prove high-accuracy signal transmission and clean switching quality. This QPA design offers a power-efficient solution with better performance characteristics that makes it an attractive candidate for the future 5G communication systems that are to operate in the 5.8 GHz frequency band.