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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 456 Documents
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Research, challenges and opportunities in software define radio technologies Jacob Abraham; Kanagaraj Venusamy; Antony Judice; Joel Livin A. Obtained; Hameed Shaik; Kannadhasan Suriyan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp260-268

Abstract

The network extended not just internationally but also throughout a broad variety of application areas in this age, with healthcare being one of the most well-known and vital industries. Improvements in healthcare are possible if we start using the popular internet of things (IoT) technology as a key instead of focusing on other disciplines. Wireless body area network (WBAN) is a field in which we communicate with a network of human people and medical equipment that may be used in conjunction with internet of things technology to perform any function. Additional features for software defined networks will be added in the future. In the event of a critical crisis, the suggested suggestions will be to take care of the patient's life. Because the fitted equipment keeps a lot better eye on the patient than previously advised methods. This study combines WBAN, IoT, and software defined network (SDN) to make sense in the healthcare field.
FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm Nithya Ramalingam; Anitha Thiagarajan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp157-164

Abstract

The proposed method involves the fault analysis of the inverter switches present in the multi-level inverter (MLI) circuitry. The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. The multi-level inverter utilized in this work is a 7-level switched ladder multi-level inverter. There is 4 number of switches in the design of a 7-level inverter driven by the non-carrier digital pulse width modulation signals. The non-carried-based digital pulse-width modulator (DPWM) generation is generated using the event angle for the 7-level of the switched ladder inverter. The proposed method investigates the stuck-at-fault occurrences of the 4 switches in the inverter by manipulating the decision tree parameters such as entropy, information gain, and decision tree. Based on the decision tree, the very high-speed integrated circuit hardware description language (VHDL) code is developed by making use of the behavioral modeling and validated for the power, area in the Xilinx Vivado tool. The real-time feasibility is verified for the proposed method by synthesizing the developed VHDL code in the field programmable gate array (FPGA) device.
Analysis of frequency dependent Vedic chanting and its influence on neural activity of humans Veera Raghava Swamy Nalluri; V. J. K. Kishor Sonti; G. Sundari
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp230-239

Abstract

In this paper a novel methodology is proposed to identify and to compare the frequency range of different Vedic chantings from Rig Veda, Yajur Veda, Atharva Veda and Sama Veda. Nowadays in spite of busy schedule and hectic work, the human beings are mostly stressed. To get rid from this stressed state, one of the best solutions is listening Vedic chantings. The alpha brainwaves are in the frequency range of 8-12 Hz under giving relaxation to stressed human being. Three selected samples from each Veda have been processed through the simulation compiler Praat and the parameters like spectral response, pitch, intensity, formants and pulses have observed. In the above identified parameters, the frequency in intensity calculation is taken for each sample. This frequency is compared with the brainwaves for which the frequencies are in the ranges of 0 Hz to >27 Hz (alpha, beta, gamma, theta and delta). The extracted signal frequencies from Vedic chantings are compared with frequencies of brainwaves. Among the four Vedas, the frequencies extracted from Sama Veda lies in alpha frequency range. The remaining is fluctuating from alpha.
Video saliency-detection using custom spatiotemporal fusion method Warad, Vinay C.; Fatima, Ruksar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp269-275

Abstract

There have been several researches done in the field of image saliency but not as much as in video saliency. In order to increase precision and accuracy during compression, reduce coding complexity and time consumption along with memory allocation problems with our proposed solution. It is a modified high-definition video compression (HEVC) pixel based consistent spatiotemporal diffusion with temporal uniformity. It involves taking apart the video into groups of frames, computing colour saliency, integrate temporal fusion, pixel saliency fusion is conducted and then colour information guides the diffusion process for the spatiotemporal mapping with the help of permutation matrix. The proposed solution is tested on a publicly available extensive dataset with five global saliency valuation metrics and is compared with several other state-of-the-art saliency detection methods. The results display and overall best performance amongst all other candidates.
A novel reduced instruction set computer-communication processor design using field programmable gate array Joseph Anthony Prathap; Sai Ramesh
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp165-173

Abstract

In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift register are included in the design. The pipeline mechanism is incorporated in the design to enhance the performance characteristics of the processor, hence allowing the execution of the instructions more effectively. Also, the design is implemented with Xilinx Virtex 7 family FPGA. The device utilization analysis of the proposed FPGA along with different FPGA families is evaluated and compared.
Optimized load balancing mechanism in parallel computing for workflow in cloud computing environment Asma Anjum; Asma Parveen
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp276-286

Abstract

Cloud computing gives on-demand access to computing resources in metered and powerfully adapted way; it empowers the client to get access to fast and flexible resources through virtualization and widely adaptable for various applications. Further, to provide assurance of productive computation, scheduling of task is very much important in cloud infrastructure environment. Moreover, the main aim of task execution phenomena is to reduce the execution time and reserve infrastructure; further, considering huge application, workflow scheduling has drawn fine attention in business as well as scientific area. Hence, in this research work, we design and develop an optimized load balancing in parallel computation aka optimal load balancing in parallel computing (OLBP) mechanism to distribute the load; at first different parameter in workload is computed and then loads are distributed. Further OLBP mechanism considers makespan time and energy as constraint and further task offloading is done considering the server speed. This phenomenon provides the balancing of workflow; further OLBP mechanism is evaluated using cyber shake workflow dataset and outperforms the existing workflow mechanism.
Efficient content-based image retrieval using integrated dual deep convolutional neural network Feroza D. Mirajkar; Ruksar Fatima; Shaik A. Qadeer
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp297-304

Abstract

Content-based image retrieval (CBIR) uses the content features for retrieving and searching the images in a given large database. Earlier, different hand feature descriptor designs are researched based on cues that are visual such as shape, colour, and texture used to represent these images. Although, deep learning technologies have widely been applied as an alternative to designing engineering that is dominant for over a decade. The features are automatically learnt through the data. This research work proposes integrated dual deep convolutional neural network (IDD-CNN), IDD-CNN comprises two distinctive CNN, first CNN exploits the features and further custom CNN is designed for exploiting the custom features. Moreover, a novel directed graph is designed that comprises the two blocks i.e. learning block and memory block which helps in finding the similarity among images; since this research considers the large dataset, an optimal strategy is introduced for compact features. Moreover, IDD-CNN is evaluated considering the two distinctive benchmark datasets the oxford dataset considering mean average precision (mAP) metrics and comparative analysis shows IDD-CNN outperforms the other existing model.
Development of IoTs-based instrument monitoring application for smart farming using solar panels as energy source Yovanka Davincy Setiawan; Bryan Ghilchrist; Gerry Giovan; Mochammad Haldi Widianto
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp248-259

Abstract

Indonesia is currently carrying out an industrial revolution 4.0. This revolution discusses the application of technology in the industrial sector, one of which is the agricultural sector. In addition to discussing the application of technology, this revolution also supports the use of renewable energy sources and one of them is the application of solar energy. The application of technology in the agricultural sector is expected to help farmers in maintaining crops to reduce the possibility of crop failure. The existence of this statement makes researchers conduct research in the design and construction of systems with internet of things (IoT) technology and utilize solar energy sources as energy sources for the system. The IoT system will utilize the ATmega328P+ESP8266 RobotDyn microcontroller by utilizing the DHT22, MD0127, soil moisture sensor, and BH1750FVI sensors and sending data to Thingspeak by utilizing the internet network with HTTP communication protocols. The system can monitor ecological factors in gardens with a fairly good degree of accuracy and the utilization of solar energy can run the system properly.
Adaptive filters based efficient EEG classification for steady state visually evoked potential based BCI system Manjula Krishnappa; Madaveeranahally Boregowda Anandaraju
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp215-221

Abstract

Brain-computer interfaces (BCIs) system is a link to generate a communication between disable people and physical devices. Thus, steady state visually evoked potential (SSVEP) is analysed to improve performance efficiency of BCIs system using multi-class classification process. Thus, an adaptive filtering-based component analysis (AFCA) method is adopted to examine SSVEP from multiple-channel electroencephalography (EEG) signals for BCIs system efficiency enhancement. Further, flickering at varied frequencies is used in a visual stimulation process to examine user intentions and brain responses. A detailed solution for optimization problem and efficient feature extraction is also presented. Here, a large SSVEP dataset is utilized which contains 256 channel EEG data. Experimental results are evaluated in terms of classification accuracy and information transfer rate to measure efficiency of proposed SSVEP extraction method against varied traditional SSVEP-based BCIs. The average information transfer rate (ITR) results are 308.23 bits per minute and classification accuracy is 93.48% using proposed AFCA method. Thus, proposed AFCA method shows decent performance in comparison with state-of-art-SSVEP extraction methods.
Reconfigurable linear feedback shift register for wireless communication and coding Aakanksha Devrari; Adesh Kumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp195-204

Abstract

Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. The LFSR is used in chip hardware for high-speed operations, error control, and the generation of pseudo-random numbers. The hardware chip design and performance estimation of the LFSR is the problem for specific communication system. The motivation of the work is to generate the Gold code sequence by the integration of two LFSR. The article proposes the hardware chip design and simulation of two 5-bit LFSR modules used for the gold sequence generator applicable for the communication systems. The novelty of the work is that the design is scalable and can be extended based on the requirements of the systems which is synthesized and experimentally verified on the Zynq-7000 field programmable gate array (FPGA) board. The concept of this design is programmable and can be extended to n-bit based on the applications. The work is supported, and formulated using very high speed integrated circuit hardware description language (VHDL) programming in Xilinx ISE 14.7 software.

Page 27 of 46 | Total Record : 456

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