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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 456 Documents
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Ultra-low leakage static random access memory design Didigam Anitha; Mohd. Masood Ahmad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 1: March 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i1.pp60-69

Abstract

An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T SRAM cells, leakage power of the proposed cell in hold mode reduced significantly. The stability parameters of the proposed cell are calculated using butterfly method and also N-curve method. Proposed SRAM achieves better write margin with slightly less read margin than 6T SRAM. Proposed technique consumes 790 PW of power in hold mode, which is very less compared to other existing techniques. Therefore, the proposed cell is appropriate for hold mode applications. The simulations are carried out by using Cadence (Virtuoso Schematic and layout editor) tools with GPDK45-nm technology.
Effects of wood texture and color on aesthetic pleasure: two experimental studies Zetian Dai; Juan Xue; Shoushan Wang
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 1: March 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i1.pp125-134

Abstract

The texture and color on wood are key factors that influence an individual's perception of it. However, little research has been done to confirm what kind of pattern in textures and colors are more likely to evoke individual aesthetic pleasure. Therefore, twenty-four decorative wood from northern China were selected, identified, and quantified in their colors with a CR-5 Colorimeter. We picked out eight kinds of wood with optimal texture characteristics through feature-fusion wood grain recognition (FWGR) and enhanced the texture features with photoshop in VR space. The result show that, in the color dimension, woods in the hue range of 20-25 and saturation of 65-75 were considered beautiful for individual perception of aesthetic. In the texture dimension, the size of the space affects the individual's preference for texture. When the pattern of the wood ray is continuous and clear, the individual's perception of its fluidity is enhanced; while for the fuzzy and interrupted pattern of the wood ray, the individual does not follow the fluidity of the line but focuses on the overall uniformity.
Application of artificial intelligence techniques in the intensive care unit Prabhudutta Ray; Sachin Sharma; Raj Raval
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 1: March 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i1.pp42-50

Abstract

Intensive care unit deals with data that are dynamic in nature like real time measurement of health condition to laboratory test data that are continuously changes accordingly with time. Artificial intelligence (AI’s) potential ability to perform complex pattern analyses using large volumes of data. Generated pattern discovers the new symptoms of the disease in the Intensive care units (ICUs), helps the doctors to prescribe the new drug discovery which is helpful to intelligent use. Currently research work has been focused in the ICU making more efficient clinical workflow by generation of high-risk patterns from improved high volumes of data. Emerging area of AI in the ICU includes mortality prediction, uses of powerful sensors, new drug discovery, prediction of length of stay and legal role in uses of drugs for severity of disease. This review focuses latest application of AI drugs and other relevant issues for the ICU.
A systematic literature review on hardware implementation of image processing Zul Imran Azhari; Samsul Setumin; Anis Diyana Rosli; Siti Juliana Abu Bakar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 1: March 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i1.pp19-28

Abstract

Image processing has become under the spotlight recently and leads to a significant shift in various fields such as biomedical, satellite images, and graphical applications. Nevertheless, the poor quality of an image is one of the noticeable limitations of image processing as it restricts efficient data extraction to be conducted. Conventionally, the image was processed via software applications such as MATLAB. In spite of the software's ability to cater to the data extraction of low-quality image issues, it still suffers from the time-consuming issue. As the ability to obtain a rapid outcome is a favorable feature of efficient image processing, the use of hardware in image processing is deemed to keep the addressed issue at bay. Thus, the image enhancement techniques using hardware have gradually rising interest among researchers with numerous approaches such as field programmable gate array (FPGA). In this study, 25 different research papers published from 2016 to 2021 are studied and analyzed to focus on the performance of FPGA as hardware implementation in image processing techniques.
SDSFLF: fault localization framework for optical communication using software digital switching network Chitra Raju; Sudarmani Rajagopal; Kanagaraj Venusamy; Kannadhasan Suriyan; Manjunathan Alagarsamy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 1: March 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i1.pp113-124

Abstract

Optical network is an emerging technology for data communication inworldwide. The information is transmitted from the source to destination through the fiber optics. All optical network (AON) provides good transmission transparency, good expandability, large bandwidth, lower bit error rate (BER), and high processing speed. Link failure and node failure haveconsistently occurred in the traditional methods. In order to overcome the above mentioned issues, this paper proposes a robust software defined switching enabled fault localization framework (SDSFLF) to monitor the node and link failure in an AON. In this work, a novel faulty node localization (FNL) algorithm is exploited to locate the faulty node. Then, the software defined faulty link detection (SDFLD) algorithm that addresses the problem of link failure. The failures are localized in multi traffic stream (MTS) and multi agent system (MAS). Thus, the throughput is improved in SDSFLF compared than other existing methods like traditional routing and wavelength assignment (RWA), simulated annealing (SA) algorithm, attackaware RWA (A-RWA) convex, longest path first (LPF) ordering, and biggest source-destination node degree (BND) ordering. The performance of the proposed algorithm is evaluated in terms of network load, wavelength utilization, packet loss rate, and burst loss rate. Hence, proposed SDSFLF assures that high performance is achieved than other traditional techniques.
Turbo encoder and decoder chip design and FPGA device analysis for communication system Aakanksha Devrari; Adesh Kumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp174-185

Abstract

Turbo codes are error-correcting codes with performance that is close to the Shannon theoretical limit (SHA). The motivation for using turbo codes is that the codes are an appealing mix of a random appearance on the channel and a physically realizable decoding structure. The communication systems have the problem of latency, fast switching, and reliable data transfer. The objective of the research paper is to design and turbo encoder and decoder hardware chip and analyze its performance. Two convolutional codes are concatenated concurrently and detached by an interleaver or permuter in the turbo encoder. The expected data from the channel is interpreted iteratively using the two related decoders. The soft (probabilistic) data about an individual bit of the decoded structure is passed in each cycle from one elementary decoder to the next, and this information is updated regularly. The performance of the chip is also verified using the maximum a posteriori (MAP) method in the decoder chip. The performance of field-programmable gate array (FPGA) hardware is evaluated using hardware and timing parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers a better global rate for the same component code performance, and reduced delay, low hardware complexity, and higher frequency support.
Development of magnetic levitation system with position and orientation control Siti Juliana Abu Bakar; Koay J-Shenn; Patrick Goh; Nur Syazreen Ahmad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp287-296

Abstract

This work demonstrates the design and development of a magnetic levitation (MagLev) system that is able to control both the position and orientation of the levitated object. For the position control, a pole placement method was exploited to estimate parameters of the proportional integral derivative (PID) controller. In addition, the MagLev was constructed using a pair of electromagnets, two infrared (IR) receiver-emitter pairs and a servo motor to allow the orientation of the object to be controlled. The proposed controller was programmed in a LabVIEW environment, which was then compiled and deployed into an embedded NI myRIO board. Experimental results demonstrated that the proposed method was able to achieve a zero steady-state orientation error when the object was rotated from 0 ◦ to ±90◦ , a steady-state position error of 0.3 cm without rotation, and steady-state position errors of no greater than 1.2 cm with rotation.
Automated ventilator prototype for COVID-19 patient treatment: the design and development of the electronic system Adrián Stacul; Daniel Pastafiglia; Ariel Dalmas Di Giovanni; Martín Morales; Sergio Saluzzi; Gerardo García
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp222-229

Abstract

The coronavirus disease 2019 (COVID-19) pandemic has created an urgent global demand for ventilators, respirators and various resuscitation devices. Various research and development organizations, private companies and individual engineers have collaborated and carried out the development of low-cost ventilation prototypes. In turn, doctors and nurses are collapsed due to the exponential increase in COVID-19 cases. This scenario worsens more when the tasks are manual in nature. The article`s objective to describe the electronic system designed, developed and implemented in a functional prototype of an automatic ventilator in order to be evaluated by a team of health professionals to be later used in cases of health emergencies. This system automates the manual ventilation task aided by a few medical resources in a scenario of scarce resources and is a temporary solution when a respirator is not available.
S11 parameter results comparison in reconfigurable antennas under simulation and measurement V. Reji; C. T. Manimegalai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp186-194

Abstract

In this paper, a simulation and measurement return loss parameter results comparison in frequency reconfigurable antenna is proposed. More lowprofile and compact microstrip antennas have been developed in recent years for 5 GHz, 5G, WLAN, Wi-Fi, and ISM band applications. These antenna frequency bands may be single, dual, or multiband. The small microstrip antenna, without connecting any external devices like switches, resonators, and passive elements, does not show any variations in their simulation and measurement results like return loss (S11 parameter), gain, and efficiency. However, in the S11 parameter most frequency reconfigurable antennas show a mismatch between simulation and measurement results. The reason for this mismatch between the simulation and measurement results are given in the paper.
Heart failure prediction based on random forest algorithm using genetic algorithm for feature selection Yudi Ramdhani; Cakra Mahendra Putra; Doni Purnama Alamsyah
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 2: July 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i2.pp205-214

Abstract

A disorder or illness called heart failure results in the heart becoming weak or damaged. In order to avoid heart failure early on, it is crucial to understand the causes of heart failure. Based on validation, two experimental processing steps will be applied to the dataset of clinical records related to heart failure. Testing will be done in the first step utilizing six different classification algorithms, including K-nearest neighbor, neural network, random forest, decision tree, Naïve Bayes, and support vector machine (SVM). Cross-validation was employed to conduct the test. According to the results, the random forest algorithm performed better than the other five algorithms in tests employing the algorithm. Subsequent testing uses an algorithm with the best accuracy value, which will then be tested again using split validation with varying split ratios and genetic algorithms as a selection feature. The value generated from testing using the genetic algorithm selection feature is better than the random forest algorithm alone, which is recorded to produce an accuracy value of 93.36% in predicting the survival of heart failure patients.

Page 26 of 46 | Total Record : 456

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