International Journal of Electrical and Computer Engineering
International Journal of Electrical and Computer Engineering (IJECE, ISSN: 2088-8708, a SCOPUS indexed Journal, SNIP: 1.001; SJR: 0.296; CiteScore: 0.99; SJR & CiteScore Q2 on both of the Electrical & Electronics Engineering, and Computer Science) is the official publication of the Institute of Advanced Engineering and Science (IAES). The journal is open to submission from scholars and experts in the wide areas of electrical, electronics, instrumentation, control, telecommunication and computer engineering from the global world.
Articles
6,301 Documents
The Security of Arithmetic Compression Based Text Steganography Method
Reihane Saniei;
Karim Faez
International Journal of Electrical and Computer Engineering (IJECE) Vol 3, No 6: December 2013
Publisher : Institute of Advanced Engineering and Science
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Security of a modern design of steganography on lossless compression isstudied in this paper. Investigation of a set of methods presented hereindicates that there are various approaches to establish a hidden and saferelationship with the minimum cost for text files. Although, steganography of information in text is one of the most difficult areas of steganography, many efforts were made in this regard. With regard to the spread of this category and existence of wide volume of approaches, this paper deals with comparison and evaluation of steganography security by a statisticalcompression method called arithmetic coding and other methods of textsteganography. Moreover, this method is available for audio-visual and video files. In addition, stego key was placed in a format that it would not arouse any suspicions. It is notable that this new method of steganography or rewriting and syntactic and semantic review does not reveal the secret message and results in 82.88% improvement in security.DOI:http://dx.doi.org/10.11591/ijece.v3i6.4068
Tree Based Energy Balancing Routing Protocol by Self Organizing in Wireless Sensor Networks
Syed Umar;
P.V.R. D Prasada Rao;
Sridevi Gutta
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 6: December 2015
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v5i6.pp1486-1491
Today the wireless sensor networks (WSN) play a crucial role in wireless technology in various domains like military, medicine, communications etc. The energy conservation is the crucial factor in the WSN. The WSN is a system which has more number of nodes in which various sensors are fabricated on the nodes to monitor various factors of the given task. These nodes will form a network by connecting the one to other for the effective communication between the nodes, and sends the whole information to the base station (BS). As the nodes which we use for the WSN are of low cost and are battery operated. The main drawback is replacement of the battery in the WSN. The main goal is to conserve the energy consumption in WSN and also to balance the load on WSN. For this many protocols are designed like LEACH, PEGASIS, PEDAP, etc. in those balancing the load and time delayed. some drawbacks are there. So we proposed a protocol so called “Tree Based Energy Balancing routing Protocol by Self Organizing” (TEBRSO), in which instead of routing tables a routing tree will be used for routing from nodes to base station (BS), which chooses one root/control node for the broadcasting messages to the selected sensor nodes. By this protocol we can save the energy consumption in WSN and can extend the life time of it. The performance of this protocol is better when we compare with other energy saving protocols.
Proposal and design methodology of switching mode low dropout regulator for Bio-medical applications
Kenya Kondo;
Hiroki Tamura;
Koichi Tanno
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 6: December 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v9i6.pp5046-5059
The switching operation based low dropout (LDO) regulator utilizing on-off control is pre-sented. It consists of simple circuit elements which are comparator, some logic gates, switched capacitor and feedback circuit. In this study, we target the application to the power supply circuit for the analog front end (AFE) of bio-medical system (such as daily-used bio-monitoring devices) whose required maximum load current is 50 A. In this paper, the design procedure of the proposed LDO has been clarified and actual circuit design using the procedure has been done. The proposed LDO has been evaluated by SPICE simulation using 1P 2M 0.6 m CMOS process device parameters. From simulation results, we could confirm that the low quiescent current of 1 A with the output ripple of 5 mVpp. The circuit area is 0.0173 mm2 in spite of using 0.6 m design rules. The proposed circuit is suitable for adopting to the light load and low frequency applications.
Development of a Spatial Path-Analysis Method for Spatial Data Analysis
Wiwin Sulistyo;
Subanar Subanar;
Reza Pulungan
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 4: August 2018
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v8i4.pp2456-2467
Path analysis is a method used to analyze the relationship between independent and dependent variables to identify direct and indirect relationship between them. This method is developed by Sewal Wright and initially only uses correlation analysis results in identifying the variables' relationship. Path analysis method currently is mostly used to deal with variables with non-spatial data type. When analyzing variables that have elements of spatial dependency, path analysis could result in a less precise model. Therefore, it is necessary to build a path analysis model that is able to identify and take into account the effects of spatial dependencies. Spatial autocorrelation and spatial regression methods can be used to develop path analysis method so as to identify the effects of spatial dependencies. This paper proposes a method in the form of path analysis method development to process data that have spatial elements. This study also discusses our effort on establishing a method that could be used to identify and analyze the spatial effect on data in the framework of path analysis; we call this method spatial path analysis.
Modeling, Simulation, and Optimal Control for Two-Wheeled Self-Balancing Robot
Modestus Oliver Asali;
Ferry Hadary;
Bomo Wibowo Sanjaya
International Journal of Electrical and Computer Engineering (IJECE) Vol 7, No 4: August 2017
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v7i4.pp2008-2017
Two-wheeled self-balancing robot is a popular model in control system experiments which is more widely known as inverted pendulum and cart model. This is a multi-input and multi-output system which is theoretical and has been applied in many systems in daily use. Anyway, most research just focus on balancing this model through try-on experiments or by using simple form of mathematical model. There were still few researches that focus on complete mathematic modeling and designing a mathematical model based controller for such system. This paper analyzed mathematical model of the system. Then, the authors successfully applied a Linear Quadratic Regulator (LQR) controller for this system. This controller was tested with different case of system condition. Controlling results was proved to work well and tested on different case of system condition through simulation on matlab/Simulink program.
Priority based round robin (PBRR) CPU scheduling algorithm
Sonia Zouaoui;
lotfi boussaid;
abdellatif mtibaa
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 1: February 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v9i1.pp190-202
This paper introduce a new approach for scheduling algorithms which aim to improve real time operating system CPU performance. This new approach of CPU Scheduling algorithm is based on the combination of round-robin (RR) and Priority based (PB) scheduling algorithms. This solution maintains the advantage of simple round robin scheduling algorithm, which is reducing starvation and integrates the advantage of priority scheduling. The proposed algorithm implements the concept of time quantum and assigning as well priority index to the processes. Existing round robin CPU scheduling algorithm cannot be dedicated to real time operating system due to their large waiting time, large response time, large turnaround time and less throughput. This new algorithm improves all the drawbacks of round robin CPU scheduling algorithm. In addition, this paper presents analysis comparing proposed algorithm with existing round robin scheduling algorithm focusing on average waiting time and average turnaround time.
Comparison of coherent optical transmission systems performance by DP-QAM levels
Abdul Gafur;
M.S. Islam;
Syed Zahidur Rashid
International Journal of Electrical and Computer Engineering (IJECE) Vol 10, No 3: June 2020
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v10i3.pp2513-2522
In this paper, we investigated the Coherent Optical Transmission System (COTS) performance for multiple types of DP-QAM levels considering various CW laser input power. We compared the performance of COTS for 100 Gb/s with DP-32QAM, DP-64QAM and DP-128QAM respectively. We also inspected the relationship among Optical Signal to Noise Ratio (OSNR), Error Vector Magnitude (EVM) and Bit Error Rate (BER) which are found in accordance for both simulation curves and constellation diagrams. Results are obtained by experiments with DP-32QAM, DP-64QAM and DP-128QAM modulations techniques at symbol rate of 10 Gsymbol/s, 8.33 Gsymbol/s and 7.142 Gsymbol/s respectively. This work is completely based on simulation in Optisystem simulation setup.
Tip Speed Ratio Based MPPT Algorithm and Improved Field Oriented Control for Extracting Optimal Real power and Independent Reactive Power Control for Grid Connected Doubly Fed Induction Generator
D.V.N. Ananth;
Gundavarapu Venkata Nagesh Kumar
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 3: June 2016
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v6i3.pp1319-1331
Doubly Fed Induction Generator (DFIG) needs to get adopted to change in wind speeds with sudden change in reactive power or grid terminal voltage as it is required for maintaining synchronism and stability as per modern grid rules. This paper proposes a controller for DFIG converters and optimal tip speed ratio based maximum power point tracking (MPPT) for turbine to maintain equilibrium in rotor speed, generator torque, and stator and rotor voltages and also to meet desired reference real power during the turbulences like sudden change in reactive power or voltage with concurrently changing wind speed. The performance of DFIG is compared when there is change in wind speed only, changes in reactive power and variation in grid voltage along with variation in wind speed.
Simulation and Implementation of a High Performance Torque Control Scheme of IM Utilizing FPGA
R. Rajendran;
N. Devarajan
International Journal of Electrical and Computer Engineering (IJECE) Vol 2, No 3: June 2012
Publisher : Institute of Advanced Engineering and Science
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Thi paper presents a novel approach to design and implementation of a high perfromane torque control scheme i.e. direct torque control with space vector modulation(DTC-SVM) of three phase induction motor using Field Programmable gate array (FPGA). The conventional direct torque control (DTC) is one of control scheme that is used commonly in induction motor control system. This method supports a very quick and precise torque response. However, the conventional DTC is not perfect and has some disadvantages. To minimize the ripples of the electromagnetic torque and flux linkage and to fix the variable switching frequency produced in the conventional DTC, this paper proposes improved DTC-SVM concept. Both simulation and experimental results show that the proposed scheme can dramatically improve the steady state performance while preserving the dynamic performance of the conventional DTC.DOI:http://dx.doi.org/10.11591/ijece.v2i3.208
Processor Speed Control for Power Reduction of Real-Time Systems
Medhat Awadalla
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 4: August 2015
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/ijece.v5i4.pp701-713
Reducing energy consumption is a critical issue in the design of battery-powered real time systems to prolong battery life. With dynamic voltage scaling (DVS) processors, energy consumption can be reduced efficiently by making appropriate decisions on the processor speed/voltage during the scheduling of real time tasks. Scheduling decision is usually based on parameters which are assumed to be crisp. However, in many circumstances the values of these parameters are vague. The vagueness of parameters suggests that to develop a fuzzy logic approach to reduce energy consumption by determining the appropriate supply-voltage/speed of the processor provided that timing constraints are guaranteed. Intensive simulated experiments and qualitative comparisons with the most related literature have been conducted in the context of dependent real-time tasks. Experimental results have shown that the proposed fuzzy scheduler saves more energy and creates feasible schedules for real time tasks. It also considers tasks priorities which cause higher system utilization and lower deadline miss time.