International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
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<![CDATA[Implementation of first order statistical processor on FPGA for feature extraction ]]>
<![CDATA[Hadiyoso, Sugondo]]>;
<![CDATA[Ramdani, Ahmad Zaky]]>;
<![CDATA[Irawati, Indrarini Dyah]]>;
<![CDATA[Wijayanto, Inung]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp234-243
<![CDATA[Statistical calculations on signals commonly used in feature extraction. In software processing, statistical computation is an easy task. However, providing a computer requires high costs for simple statistical processing. Another consideration is the need for implementation with real-time and portable processing. Therefore, an alternative device is needed, one of which is the field programmable gate array (FPGA). FPGA is a logic circuit board that can be reconfigured according to computing needs. FPGA can also be used as a prototyping of electronic chips. However, implementing statistical formulas in FPGA is interesting in developing its architecture. Therefore, this research proposes a logic circuit design that can be used for first-order statistical calculations. Statistical parameters include the mean, variance, standard deviation, skewness, and kurtosis. The validation test was performed on the electrocardiogram (ECG) signal series and compared with manual calculations. Validation shows that the mean and variance has very high accuracy with an average error of less than 0.06%.]]>
<![CDATA[Artificial intelligence-powered intelligent reflecting surface systems countering adversarial attacks in machine learning ]]>
<![CDATA[Muthusamy, Rajendiran]]>;
<![CDATA[Kannan, Charulatha]]>;
<![CDATA[Mani, Jayarathna]]>;
<![CDATA[Govindharajan, Rathinasabapathi]]>;
<![CDATA[Ayyasamy, Karthikeyan]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp414-423
<![CDATA[With the increase in the computation power of devices wireless communication has started adopting machine learning (ML) techniques. Intelligent reflecting surface (IRS) is a programmable device that can be used to control electromagnetic wave propagation by changing the electric and magnetic values of its surface. State-of-the-art ML especially on deep learning (DL)-based IRS-enhanced communication is an emerging topic. Yet while integrating IRS with other emerging technologies possibilities of adversarial data creaping is high. Threats to security, their mitigation, and complexes for AI-powered applications in next generation networks are continuously emerging. In this work the ability of an IRS enhanced wireless network in future-generation networks to prevent adversarial machinelearning attacks is studied. The artificial intelligence (AI) model is used to minimize the susceptibility of attacks using defense distillation mitigation technique. The outcome shows that the defensive distillation technique (DDT) increases the strength and performance by around 22% of the AI method under an adversarial attack.]]>
<![CDATA[A condition-based distributed approach for secured privacy preservation of nodes in wireless sensor networks IoT ]]>
<![CDATA[Kumara, Bharat]]>;
<![CDATA[Padmanabhan, S. Anantha]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp441-449
<![CDATA[The fast expansion of wireless sensor network-internet of things (WSN-IoT) in recent years has led to the adoption of a vital infrastructure. Adversaries who work together to carry out privacy-related attacks and capture sensitive information from critical infrastructure for a range of personal, political, and commercial purposes, thus security and node preserving have been one of the key areas of research in WSN-IoT. Existing security and privacy research work focuses on cryptography, either which is less efficient, or it majorly focuses on securing the network, which further leads to exposing the nodes to the vulnerability in terms of privacy in the network. This research develops condition-based distributed privacy-preserving (CDPP) approach to preserve the sensor node privacy; the CDPP algorithm develops a condition based on which the nodes' vulnerable information is preserved and not accessed by the compromised nodes. CDPP architecture is evaluated considering the amount of misclassified nodes for safeguarding the node in the network. CDPP is evaluated by inducing the corrupt nodes and further comparing the model with existing low energy adaptive clustering hierarchy (LEACH) based on classification, misclassification and throughput. Furthermore, comparative analysis proves the marginal improvisation in terms of discussed parameter against existing protocol.]]>
<![CDATA[Deep learning-based channel estimation with application to 5G and beyond networks ]]>
<![CDATA[Jayashankar, Parinitha]]>;
<![CDATA[Nanjundaiah, Shobha Byrappa]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp271-277
<![CDATA[Channel state information (CSI) feedback estimation for a downlink medium in a massive multiple input multiple output (MIMO) system is an essential and critical task to improve channel capacity and performance yield, especially in a frequency division duplex (FDD) multiplexing system. However, spectral efficiency degradation is a massive issue due to high channel feedback overhead. This work proposes a deep learning-based channel estimation (DLCE) model to improve channel reconstruction efficiency and channel overhead reduction accuracy. The proposed deep learning (DL) mechanism consists of encoder and decoder network where encoder network is utilized to compress CSI matrices whereas decoder network is used to decompress obtained CSI matrices. Here, inverse discrete Fourier transform (IDFT) method is utilized to convert CSI matrices of frequency domain into CSI matrices of delay domain. Simulation results are evaluated between uplink and downlink medium in the massive MIMO system considering a co-operation in science and technology (COST) 2,100 model. Here, a significant improvement in correlation and normalized mean square error (NMSE) results is observed. The proposed DLCE model shows superior performance against varied channel estimation techniques in terms of NMSE and correlation efficiency.]]>
<![CDATA[Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications ]]>
<![CDATA[Siva Kumar, Malagonda]]>;
<![CDATA[Mohanraj, Jayavelu]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp307-314
<![CDATA[Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.]]>
<![CDATA[An efficient novel dual deep network architecture for video forgery detection ]]>
<![CDATA[Chandrakala, Chandrakala]]>;
<![CDATA[Sasikala, Mungamuri]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp458-471
<![CDATA[The technique of video copy-move forgery (CMF) is commonly employed in various industries; digital videography is regularly used as the foundation for vital graphic evidence that may be modified using the aforementioned method. Recently in the past few decades, forgery in digital images is detected via machine intellect. The second issue includes continuous allocation of parallel frames having relevant backgrounds erroneously results in false implications, detected as CMF regions third include as the CMF is divided into inter-frame or intra-frame forgeries to detect video copy is not possible by most of the existing methods. Thus, this research presents the dual deep network (DDN) for efficient and effective video copy-move forgery detection (VCMFD); DDN comprises two networks; the first detection network (DetNet1) extracts the general deep features and second detection network (DetNet2) extracts the custom deep features; both the network are interconnected as the output of DetNet1 is given to DetNet2. Furthermore, a novel algorithm is introduced for forged frame detection and optimization of the falsely detected frame. DDN is evaluated considering the two benchmark datasets REWIND and video tampering dataset (VTD) considering different metrics; furthermore, evaluation is carried through comparing the recent existing model. DDN outperforms the existing model in terms of various metrics.]]>
<![CDATA[FPGA in hardware description language based digital clock alarm system with 24-hr format ]]>
<![CDATA[Sayudzi, Mohd Faris Izzwan Mohd]]>;
<![CDATA[Hamzah, Irni Hamiza]]>;
<![CDATA[Malik, Azman Ab]]>;
<![CDATA[Idris, Mohaiyedin]]>;
<![CDATA[Soh, Zainal Hisham Che]]>;
<![CDATA[Rahim, Alhan Farhanah Abd]]>;
<![CDATA[Hadis, Nor Shahanim Mohamad]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp244-252
<![CDATA[Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.]]>
<![CDATA[A novel compression methodology for medical images using deep learning for high-speed transmission ]]>
<![CDATA[Navaneethakrishnan, Shyamala]]>;
<![CDATA[Shanmugam, Geetha]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp262-270
<![CDATA[Medical imaging is a rapidly growing field having a high impact on the early detection, diagnosis and surgical planning of diseases. Several imaging techniques such as computed tomography (CT), magnetic resonance imaging (MRI) and ultrasound (US) imaging generate a higher volume of data, necessitating additional storage and communication requirements. Hence, image compression is utilized in medical field to reduce redundancy and alleviate memory and bandwidth issues. This paper presents a novel deep learning-based compression method to reduce the size of medical images. This method employs a deep convolutional neural network for learning compact representations of medical images, then coded by a Huffman encoder. The compression process is reversed to reconstruct the original image. Several tests are conducted to compare the results with other wellknown compression methods. The proposed model achieved a mean peak signal-to-noise ratio (PSNR) of 42.82 dB with storage space saving (SSS) of 96.15% for CT, 43.88 dB with SSS of 96.25% for MRI, 46.29 dB with SSS of 96.07% for US and 43.51 dB with SSS of 96.95% for X-ray images. The findings showed that the proposed compression technique could greatly compress the image size, saving storage space, facilitating better transmission and preserving critical diagnostic information.]]>
<![CDATA[Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA ]]>
<![CDATA[Patil, Trupti]]>;
<![CDATA[Sandi, Anuradha M.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp296-306
<![CDATA[The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.]]>
<![CDATA[A novel ensemble deep network framework for scene text recognition ]]>
<![CDATA[Dasari, Sunil Kumar]]>;
<![CDATA[Mehta, Shilpa]]>;
<![CDATA[Steffi, Diana]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v13.i2.pp403-413
<![CDATA[In recent years, scene text recognition (STR) has always been considered a sequence-to-sequence problem. Attention-based techniques have a greater potential for context-semantic modelling, but they tend to overfit inadequate training data. STR is one of the most important and difficult challenges in image-based sequence recognition. A novel framework ensemble deep network (EDN) is proposed, EDN comprises customized convolutional neural network (CNN), and deep autoencoder. Customized CNN is designed by introducing the optimal spatial transformation module for optimizing the input of irregular text to read for same size. Further, deep autoencoder is introduced with effective attention mechanism utilizing the inherent features. The proposed ensemble deep network-proposed system (EDN-PS) approach outperforms the existing state-of-art techniques for both irregular and regular scene-texts and upon further simulations, the proposed model generates better results for IIIT5K, ICDAR-13, ICDAR-15, and CUTE dataset in comparison with the existing system hence our proposed EDN-PS model outperforms the existing state-of-art methods.]]>
