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Self-switching diodes as RF rectifiers: evaluation methods and current progress
Nor Farhani Zakaria;
Shahrir Rizal Kasjoo;
Muammar Mohamad Isa;
Zarimawaty Zailan;
Mohd Khairuddin Md Arshad;
Sanna Taking
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i2.1413
In the advancement of the Internet of Things (IoT) applications, widespread uses and applications of devices require higher frequency connectivity to be explored and exploited. Furthermore, the size, weight, power and cost demands for the IoT ecosystems also creates a new paradigm for the hardware where improved power efficiency and efficient wireless transmission needed to be investigated and made feasible. As such, functional microwave detectors to detect and rectify the signals transmitted in higher frequency regions are crucial. This paper reviewed the practicability of self switching diodes as Radio Frequency (RF) rectifiers. The existing methods used in the evaluation of the rectification performance and cut-off frequency are reviewed, and current achievements are then concluded. The works reviewed in this paper highlights the functionality of SSD as a RF rectifier with design simplicity, which may offer cheaper alternatives in current high frequency rectifying devices for application in low-power devices.
A novel optimization harmonic elimination technique for cascaded multilevel inverter
Ezzidin Hassan Aboadla;
Sheroz Khan;
Mohamed H. Habaebi;
Teddy Surya Gunawan;
Belal A. Hamida;
Mashkuri Bin Yaacob;
Ali Aboadla
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i2.1500
The main goal of utilizing Selective Harmonic Elimination (SHE) techniques in Multilevel Inverters (MLI) is to produce a high-quality output voltage signal with a minimum Total Harmonic Distortion (THD). By calculating N switching angles, SHE technique can eliminate (N-1) low order odd harmonics of the output voltage waveform. To optimized and obtained these switching angles, N of nonlinear equations should be solved using a numerical method. Modulation index (m) and duty cycle play a big role in selective harmonic elimination technique to obtain a minimum harmonic distortion and desired fundamental component voltage. In this paper, a novel Optimization Harmonic Elimination Technique (OHET) based on SHE scheme is proposed to re-mitigate Total Harmonic Distortion. The performance of seven-level H-bridge cascade inverter is evaluated using PSIM and validated experimentally by developing a purposely built microcontroller-based printed circuit board.
Task mapping and routing optimization for hard real-time Networks-on-Chip
M. Norazizi Sham Mohd Sayuti;
Farida Hazwani Mohd Ridzuan;
Zul Hilmi Abdullah
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i1.1395
Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system’s schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.
Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures
Gian Carlo Cardarilli;
Luca Di Nunzio;
Rocco Fazzolari;
Daniele Giardino;
Marco Matta;
Marco Re;
Sergio Spanò;
Lorenzo Simone
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i2.1483
In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.
Silicon carbide schottky diodes forward and reverse current properties upon fast electron radiation
M. Azim Khairi;
Rosminazuin Ab. Rahim;
Norazlina Saidin;
Yusof Abdullah;
Nurul Fadzlin Hasbullah
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i2.1503
This paper investigates on the reaction of 10 and 15MGy, 3MeV electron irradiation upon off-the-shelves (commercial) Silicon Carbide Schottky diodes from Infineon Technologies (model: IDH08SG60C) and STMicroelectronics (model: STPSC806). Such irradiation reduces the forward-bias current. The reduction is mainly due to the significant increase of the series resistance (i.e. Infineon: 1.45Ω at before irradiation → 121×103 Ω at 15MGy); STMicroelectronics: 1.44Ω at before irradiation → 2.1×109 Ω at 15MGy). This increase in series resistance gives 4.6 and 8.2 orders of magnitude reduction for the forward-bias current density of Infineon and STMicroelectronics respectively. It is also observed that the ideality factor and the saturation current of the diodes increases with increasing dose (i.e. ideality factor- Infineon: 1.01 at before irradiation → 1.05 at 15MGy; STMicroelectronics: 1.02 at before irradiation → 1.3 at 15MGy | saturation current- Infineon: 1.6×10-17A at before irradiation → 2.5×10-17A at 15MGy; STMicroelectronics: 2.4×10-15A at before irradiation → 8×10-15A at 15MGy). Reverse-bias leakage current density in model by Infineon increases by one order of magnitude after 15MGy irradiation, however, in model by STMicroelectronics decreases by one order of magnitude. Overall, for these particular samples studied, Infineon devices have shown to be better in quality and more radiation resistance toward electron irradiation in forward-bias operation while STMicroelectronics exhibit better characteristics in reverse-bias operation.
A efficacy of different buffer size on latency of network on chip (NoC)
Farah Wahida Binti Zulkefli;
P. Ehkan;
M. N. M. Warip;
Ng. Yen. Phing
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i2.1422
Moore's prediction has been used to set targets for research and development in semiconductor industry for years now. A burgeoning number of processing cores on a chip demand competent and scalable communication architecture such as network-on-chip (NoC). NoC technology applies networking theory and methods to on-chip communication and brings noteworthy improvements over conventional bus and crossbar interconnections. Calculated performances such as latency, throughput, and bandwidth are characterized at design time to assured the performance of NoC. However, if communication pattern or parameters set like buffer size need to be altered, there might result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication while routers with small buffers reduce power consumption but result in high latency. This paper intention is to validate that size of buffer exert influence to NoC performance in several different network topologies. It is concluded that the way in which routers are interrelated or arranged affect NoC’s performance (latency) where different buffer sizes were adapted. That is why buffering requirements for different routers may vary based on their location in the network and the tasks assigned to them.
Flexible PVDF thin film as piezoelectric energy harvester
Norfaizul Izwan Nordin;
Rosminazuin Ab Rahim;
Aliza Aini Md Ralib
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i2.1423
This aim of this paper is to study the potential of Polyvinylidene Fluoride (PVDF) polymeric piezoelectric film as an energy harvester for daily application use. PVDF offers several advantages over other piezoelectric materials such as high chemical strength and stability, high piezoelectric properties and biocompatible. Several investigations were carried out in this project which comprises of simulation, functionality test and application test. For functionality test, the highest voltage produced for a single film PVDF is 0.368 V which charges up a capacitor to 0.219 V in one minute. The highest voltage produced by multiple PVDF films is 1.238 V by stacking 10 films of PVDF in parallel which charges up to 0.688 V in one minute. For application test, 5 pieces of PVDF films were attached to a glove to generate some voltage during fingers bending activity. The highest output voltage recorded is 0.184 V which stores 0.101 V in a capacitor after 200 times of hand bending and releasing. As a conclusion, PVDF has a good potential as an alternative energy for daily application use. Combination of PVDF energy harvester system with proper power optimization circuit will open up rooms of research opportunities in energy harvester system with promising prospect in self-powered wireless electronics devices for Internet of Things application.
Capacitive electrode sensor implanted on a printed circuit board designed for continuous water level measurement
Salami Ifedapo Abdullahi;
Mohamed Hadi Habaebi;
Noreha Abdul Malik
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i2.1515
Water level sensors are one of the practical ways to get the actual measurement of the depth of a dam or canal. The ease of deployment and easy data acquisition makes them widely used in many fields. Therefore, it will be advantageous to have a miniaturized water level sensor for easier mobility and deployment. A novel method for measuring water level using a Printed Circuit Board has been proposed in this paper. The design stages of circuit sketching, printing of sketch on PCB and etching are discussed for the electrode water level sensor. A signal conditioning circuit is necessary to maintain a steady flow of current from the power source. The fabricated electrode water level sensor was tested based on its capacitive effect while charging up and the amount of current at each electrode finger at the saturation stage. The hardware enablers for this test were the multimeter and LCR meter. Arduino microprocessor was used to test and measure the transient response time for each electrode finger. The transient response sensitivity of the electrode sensor is measured to be 0.0873 millisecond/cm while the resolution of the electrode sensor is 0.1cm over a range of 30cm water level. A multiple correlation of 0.921 was achieved for the water level, measured current and measured capacitance with P-values less than 0.05 indicating strength of the data obtained from the tests conducted. The result showed strong evidence that the electrode water level sensor can be an alternative method of measuring water level.
Investigation on the mass sensitivity of quartz crystal microbalance gas sensor using finite element simulation
Aliza Aini Md Ralib;
Nik Nursyahida Bt Nik Mohd Zamri;
Ahmad Hafiz Faqruddin Hazadi;
Rosminazuin Ab Rahim;
Nor Farahidah Za’bah;
Norazlina Saidin
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i2.1521
The increasing global trends in healthcare priorities towards improving the effectiveness of diagnostic procedure by utilizing a non-invasive method which is breath analysis. This will benefit in increasing treatment efficiency and also reducing healthcare costs. Breath is a simple technique where the sample are easily obtained and can be provided immediately. The most popular method that had been used in hospital are urine and blood. Contradict with breath, urine and blood take too much time to analyse the disease and a painful process. The detection technique of breath analysis is done by using electroacoustic wave sensor from piezoelectric substrate. This acoustic wave sensor has been used to detect the changes in the frequency where it will be used to detect the disease. Breath analysis is a technique where it uses an electronic nose (E-nose) as a device. E-nose consist of Quartz Crystal Microbalance (QCM) sensor in order to differentiate odor in human breath. QCM is a sensitive weighing device which have a high efficiency. AT-cut quartz was chosen as the piezoelectric material and aluminum as the electrode. The objective of this paper is to design and simulate a QCM sensor for breath analysis application. Other than that, it also to determine the important key parameters that influence the performance of breath analysis which is sensitivity and resonant frequency. QCM sensor is being simulate by using COMSOL Multiphysics software. This is to evaluate the behavior of QCM sensor in terms of Eigen frequency analysis. The simulated QCM sensor with quartz radius of 166 um resonates at 8.871 MHz. The sensitivity of the sensor is 0.167 MHz/ng after exposed to acetone gas which act as the breath marker for detection of diseases in exhaled breath. Hence, the proposed design can be used as a non-invasive approach for early detection of disease through breath analysis.
Food intake gesture monitoring system based-on depth sensor
Muhammad Fuad bin Kassim;
Mohd Norzali Haji Mohd
Bulletin of Electrical Engineering and Informatics Vol 8, No 2: June 2019
Publisher : Institute of Advanced Engineering and Science
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DOI: 10.11591/eei.v8i2.1424
Food intake gesture technology is one of a new strategy for obesity people managing their health care while saving their time and money. This approach involves combining face and hand joint point for monitoring food intake of a user using Kinect Xbox One camera sensor. Rather than counting calories, scientists at Brigham Young University found dieters who eager to reduce their number of daily bites by 20 to 30 percent lost around two kilograms a month, regardless of what they ate [1]. Research studies showed that most of the methods used to count bite are worn type devices which has high false alarm ratio. Today trend is going toward the non-wearable device. This sensor is used to capture skeletal data of user while eating and train the data to capture the motion and movement while eating. There are specific joint to be capture such as Jaw face point and wrist roll joint. Overall accuracy is around 94%. Basically, this increase in the overall recognition rate of this system.