International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
456 Documents
<![CDATA[ACCESS - IoT enabled smart lock ]]>
<![CDATA[Harshith Gadupu]]>;
<![CDATA[Osa Mokharji]]>;
<![CDATA[Raunak Kankaria]]>;
<![CDATA[Shrey Kumar]]>;
<![CDATA[Kayalvizhi Jayavel]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp176-185
<![CDATA[ACCESS is a centrally controlled extensible security system - a system for enhancing accessibility and security methods. Security is an important matter of concern and everyone wants things easy and fast with the advancement of technology. Many IoT engineers are inclined towards home automation today. An area of recent interest is the automation of lock and key systems of homes and workplaces. This paper comprises mechanisms to view visitors of households, machinery, or any appliance that may be remotely controlled through a mobile application. Owners or supervisors can keep a watch on the guests and choose whom they want to grant entry to. This is conducted by providing the guests with temporary access permission for a validity period of the owner’s choice. They can also simultaneously monitor the activities of the guests.]]>
<![CDATA[Systematising troubleshooting of disputes in network ]]>
<![CDATA[Sowmya K. B.]]>;
<![CDATA[Thejaswini A.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp32-36
<![CDATA[With the growing network size, virtualization everywhere, it is getting more difficult to configure and manage the network devices. Software Defined Networking (SDN) is a way to address these problems. Application Centric Infrastructure (ACI) is the Cisco’s solution to SDN, with centralized automation and policy-driven application profiles. If there is any bug in the network or problem with the expected functionality of the network, ACI cases are opened in the Technical Assistance Centre (TAC) for troubleshooting the issue. Engineers currently troubleshoot ACI cases manually by using Command Line Interface (CLI) and trace for different events triggered by the policy pushes by logs generated at different stages of the ACI and from different servers responsible for this, which indeed is a very tedious, time consuming task and is prone to manual errors. This paper describes a way to automate the entire ACI troubleshooting process with the user-friendly GUI which can show the entire information needed for troubleshooting by extracting relevant information at every layer. By making use of FSM models the proposed solution can be extended to other areas which involve log analysis using CLI to extract relevant information and is not just limited to ACI.]]>
<![CDATA[Monolayer and bilayer graphene field effect transistor using Verilog-A ]]>
<![CDATA[Nayana G. H.]]>;
<![CDATA[Vimala P.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp56-64
<![CDATA[Monolayer and bilayer graphene field effect transistor modeling is presented in this paper. The transport model incorporated, works well for both drift diffusive and ballistic conditions. The validity of the model was checked for various device dimensions and bias voltages. Performance parameters affecting operation of graphene field effect transistor in various region of operation are optimized. Model was developed to verify transfer characteristics for monolayer and bilayer graphene field effect transistor. Results obtained prove the ambipolar property in Graphene. MATLAB is used for numerical modeling for systematic performance evaluation of parameters in graphene. The tool used to simulate the characteristics is cadence Verilog-A which describe analog component structure.]]>
<![CDATA[Smart metering system data analytics platform using multicore edge computing ]]>
<![CDATA[Juan C. Olivares-Rojas]]>;
<![CDATA[Enrique Reyes-Archundia]]>;
<![CDATA[José A. Gutiérrez-Gnecchi]]>;
<![CDATA[Ismael Molina-Moreno]]>;
<![CDATA[Adriana C. Téllez-Anguiano]]>;
<![CDATA[Jaime Cerda-Jacobo]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp11-17
<![CDATA[The smart grid revolution has only been possible, thanks to the development and proliferation of smart meters. The increasingly growing computing capabilities for Internet of Things devices have made it possible for data to be processed directly from the devices where it is produced; this has been called edge computing. Edge computing is allowing the smart grid to become increasingly intelligent to solve problems that make electricity consumption more efficient and environmentally friendly. This work presents the implementation of a smart metering system that allows data analytics using a multiprocessing architecture directly on the smart meter. The results show that the development of smart meters with data analytics capabilities at the edge is a reality today, and the use of multiprocessing permits the improvement of data processing.]]>
<![CDATA[COVID-19 paediatric cavity telecare system: a novel chain key generation and encryption scheme ]]>
<![CDATA[Joydeep Dey]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 1: March 2022 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v11.i1.pp13-24
<![CDATA[In this unprecedented coronavirus crisis, telehealth had emerged as a substitute way of treatment. More specifically, paediatric children are at high risk of outside exposure now. Non critical children must be treated remotely through the tableware system. A key based secured online transmission of an intraoral image of the paediatric cavity has been proposed in this manuscript. A cavity is a dental disease occurring in children. It is mainly caused due to prolonged bacterial infections. Secured online transmission with respect to medical transactions is immensely required in telecare information systems (TIS). Data confidentiality factor is preserved with preference in this proposed technique. A parity based novel chain key (NCK) has been generated and diffused inside the intraoral paediatric cavity image. NCK generation scheme is so highly robust that it gives different combinations after each bit altering. Initial seeds are kept at the dentist and patients, to resist myriad attacks inside the wireless channel, especially during this COVID-19 period. Histogram, floating frequency, and autocorrelation were obtained with accuracy using the proposed technique. Effects were observed by flipping simultaneous bits of the initial key and results were highly acceptable. The time for the proposed key generation has been found to be 514.61 ms. The total cryptographic time has been noted as 3.5983 ms in this technique.]]>
<![CDATA[A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST ]]>
<![CDATA[Kenta Shirane]]>;
<![CDATA[Takahiro Yamamoto]]>;
<![CDATA[Hiroyuki Tomiyama]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp1-10
<![CDATA[In this paper, we present a case study on approximate multipliers for MNIST Convolutional Neural Network (CNN). We apply approximate multipliers with different bit-width to the convolution layer in MNIST CNN, evaluate the accuracy of MNIST classification, and analyze the trade-off between approximate multiplier’s area, critical path delay and the accuracy. Based on the results of the evaluation and analysis, we propose a design methodology for approximate multipliers. The approximate multipliers consist of some partial products, which are carefully selected according to the CNN input. With this methodology, we further reduce the area and the delay of the multipliers with keeping high accuracy of the MNIST classification.]]>
<![CDATA[A PSO based optimal repeater insertion technique for Carbon Nanotube interconnects ]]>
<![CDATA[P, Uma Sathyakam]]>;
<![CDATA[Raj, Shubham]]>;
<![CDATA[Mallick, Partha S.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp%p
<![CDATA[Optimal repeater insertion is important in VLSI interconnects to reduce their propagation delay and power dissipation. We propose a particle swarm optimization (PSO) based optimal repeater number for different lengths of carbon nanotube (CNT) interconnects at 22nm and 14nm technology nodes. First, numerical equations for optimal repeaters are modelled. Secondly, a PSO based algorithm is developed and various input parameters are enlisted to train the PSO. Optimal number of repeaters and the propagation delay for CNT interconnects for lengths ranging from 500 to 2000µm are found out. Results are compared for both the methods and it is found that they are within 2% deviation. This means that PSO is an effective method to find optimum repeaters in VLSI interconnects. Though earlier works show similar findings, we have used CNTFET based inverters as drivers of CNT interconnects for the first time. Also, for two values of repeater size, i.e., h = 50 and 75, we have carried out the analysis.]]>
<![CDATA[FPGA based co-design of a speed fuzzy logic controller applied to an autonomous car ]]>
<![CDATA[Emna Aridhi]]>;
<![CDATA[Decebal Popescu]]>;
<![CDATA[Abdelkader Mami]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp195-211
<![CDATA[This paper invests in FPGA technology to control the speed of an autonomous car using fuzzy logic. For that purpose, we propose a co-design based on a novel fuzzy controller IP. It was developed using the hardware language VHDL and driven by the Zynq processor through an SDK software design written in C. The proposed IP acts according to the ambient temperature and the presence or absence of an obstacle and its distance from the car. The partitioning of the co-design tasks divides them into hardware and software parts. The simulation results of the fuzzy IP and those of the complete co-design implementation on a Xilinx Zynq board showed the effectiveness of the proposed controller to meet the target constraints and generate suitable PWM signals. The proposed hardware architecture based on 6-LUT blocks uses 11 times fewer logic resources than other previous similar designs. Also, it can be easily updated when new constraints on the system are to be considered, which makes it suitable for many related applications. Fuzzy computing was accelerated thanks to the use of digital signal processing blocks that ensure parallel processing. Indeed, a complete execution cycle takes only 7 us.]]>
<![CDATA[Enhanced MAC controller architecture for 2D processing based on FPGA with configurable resource allocation ]]>
<![CDATA[Chiranjeevi G. N.]]>;
<![CDATA[Subhash Kulkarni]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp212-220
<![CDATA[The bulks of image processing algorithms are either two-dimensional (2D) or confined by their very nature. As a result, the 2D convolution function has a large impact on picture processing requirements. The methodology of 2D convolution and media access control (MAC) design can also be used to perform a variety of image processing tasks, and even as picture blurring, softening, and feature extraction. The main goal of this research is to develop a more efficient MAC control block-based 2D convolution architecture. This 2D algorithm can be implemented in hardware using fewer modules, multipliers, adders, and control blocks, resulting in significant hardware savings and look up table (LUT) reductions. The simulations were run in Verilog, and the Xilinx Vertex family field programmable gate array (FPGA) was used to build and test them. The recommended 2D convolution architectural solution is significantly faster and consumes significantly less hardware resources than the traditional 2D convolution implementation. The proposed architecture will result in technology that saves a substantial amount of processing time when it comes to LUTs.]]>
<![CDATA[A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques ]]>
<![CDATA[Mohd Tafir Mustaffa]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp221-229
<![CDATA[Comparator is one of the main blocks that play a vital task in the performance of analog to digital converters (ADC) in all modern technology devices. High-speed devices with low voltage and low power are considered essential for industrial applications. The design of a low-power comparator with high speed is required to accomplish the requirements mostly in electronic devices that are necessary for high-speed ADCs. However, a high-speed device that leads the scaling down of CMOS process technology will consume more power. Thus, power reduction techniques such as multi-threshold super cut-off stack (MTSCStack), dual-threshold transistor stacking (DTTS), a bulk-driven, and a bulk-driven differential pair were studied in this work. This study aims to find and build the combination of these techniques to produce a comparator that can operate in low power without compromising existing performance using the 0.13-µm CMOS process. A comparator with a combination of MTSCStack, DTTS, and NMOS bulk-driven differential pair shows the most promising result of 6.29 µW for static power, 17.15 µW for dynamic power, and 23.44 µW for total power.]]>
