International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
456 Documents
<![CDATA[Heuristic algorithms for dynamic scheduling of moldable tasks in multicore embedded systems ]]>
<![CDATA[Takuma Hikida]]>;
<![CDATA[Hiroki Nishikawa]]>;
<![CDATA[Hiroyuki Tomiyama]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp157-167
<![CDATA[Dynamic scheduling of parallel tasks is one of the efficient techniques to achieve high performance in multicore systems. Most existing algorithms for dynamic task scheduling assume that a task runs on one of the multiple cores or a fixed number of cores. Existing researches on dynamic task scheduling methods have evaluated their methods in different experimental environments and models. In this paper, the dynamic task scheduling methods are systematically rearranged and evaluated.]]>
<![CDATA[A Survey of Brain Tumor Segmentation using Deep Neural Network ]]>
<![CDATA[p, karuppasamy]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp%p
<![CDATA[Tumor segmentation is an essential activity to providing intent way of predicting aggressiveness in medical image processing. Early identification of brain tumors plays a Significant part in making better treatment potential and increases the patient's lifetime. It is all important to segment the tumor, to protect healthy tissues during therapy. Manual segmentation is a complicated and prolonged procedure and improvement of automatic segmentation method afford proficient and intention segmentation. At present, automatic segmentation by means of deep learning methods proved the high-tech results. Deep learning methods for different kind of images provide robustness in segmentation. It refers to neural networks with many layers that extract a hierarchy of features from raw input images. This paper proposes to make another study of brain tumor segmentation along with the modern algorithms with current trends of deep learning algorithms are discussed.]]>
<![CDATA[FPGA implementation of Lempel-Ziv data compression ]]>
<![CDATA[Gody Mostafa]]>;
<![CDATA[Abdelhalim Zekry]]>;
<![CDATA[Hatem Zakaria]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp99-108
<![CDATA[When transmitting the data in digital communication, it is well desired that the transmitting data bits should be as minimal as possible, so many techniques are used to compress the data. In this paper, a Lempel-Ziv algorithm for data compression was implemented through VHDL coding. One of the most lossless data compression algorithms commonly used is Lempel-Ziv. The work in this paper is devoted to improve the compression rate, space-saving, and utilization of the Lempel-Ziv algorithm using a systolic array approach. The developed design is validated with VHDL simulations using Xilinx ISE 14.5 and synthesized on Virtex-6 FPGA chip. The results show that our design is efficient in providing high compression rates and space-saving percentage as well as improved utilization. The Throughput is increased by 50% and the design area is decreased by more than 23% with a high compression ratio compared to comparable previous designs.]]>
<![CDATA[Amalgam Illogical Controller Design Using Amended Moth System for Heat Reduction in Insulated Gate Bipolar Transistor ]]>
<![CDATA[Loganathan, P.]]>;
<![CDATA[Selvam, P.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp%p
<![CDATA[The electric vehicle is seen as a possible replacement for current-generation automobiles and to address the rising pollution. In electrical drives, Insulated Gate Bipolar Transistor (IGBT) modules deliver power to the motor generate a lot of heat during switching. However, heat generation in IGBT hinders the performance of the electric vehicle. The foremost existing techniques analyze the heat however does not control the heat production in the IGBT module, and also high heat density leads to failing components. Thus to reduce the heat generated in the IGBT module, the work proposed an amalgam illogical controller that handles nonlinearity and provides a quick response. This controller is further tuned by Amended Moth System (AMS) to reduce heat consumption in the IGBT module with electrical parameters. Furthermore, the IGBT is complex to excessive voltage and excessive temperature therefore the current and voltage harmonics in the inverter are reduced by a seamless genuine adaptive filter that detects and suppresses the specified harmonics in the estimated back-EMF, consequently reducing the harmonic position error in the estimated rotor position. Even though there is a problem with a wide range of frequency in the electric motor. To reduce the switching frequency supremacy harm checker is incorporated which is forced to choose active and zero voltage vectors alternatively, to decrease the variation in the switching frequency. Thus the proposed outcomes efficiently tackle the issues in EV and greatly reduce heat consumption in the IGBT module.The electric vehicle is seen as a possible replacement for current-generationautomobiles and to address the rising pollution. In electrical drives, InsulatedGate Bipolar Transistor (IGBT) modules deliver power to the motor generatea lot of heat during switching. However, heat generation in IGBT hinders theperformance of the electric vehicle. The foremost existing techniquesanalyze the heat however does not control the heat production in the IGBTmodule, and also high heat density leads to failing components. Thus toreduce the heat generated in the IGBT module, the work proposed anamalgam illogical controller that handles nonlinearity and provides a quickresponse. This controller is further tuned by Amended Moth System (AMS)to reduce heat consumption in the IGBT module with electrical parameters.Furthermore, the IGBT is complex to excessive voltage and excessivetemperature therefore the current and voltage harmonics in the inverter arereduced by a seamless genuine adaptive filter that detects and suppresses thespecified harmonics in the estimated back-EMF, consequently reducing theharmonic position error in the estimated rotor position. Even though there isa problem with a wide range of frequency in the electric motor. To reducethe switching frequency supremacy harm checker is incorporated which isforced to choose active and zero voltage vectors alternatively, to decrease thevariation in the switching frequency. Thus the proposed outcomes efficientlytackle the issues in EV and greatly reduce heat consumption in the IGBTmodule.]]>
<![CDATA[Smart helmet using internet of things ]]>
<![CDATA[Mohamed A. Torad]]>;
<![CDATA[Mustafa Abdul Salam]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp90-98
<![CDATA[The rate of death relative to the size of the world’s population has remained constant, according to the world health organization (WHO). WHO targets to minimize the ratio of road death to the half by 2022. This paper discusses a way for accident detection and notification which can decrease this ratio. Piezoelectric sensors used inside a helmet to detect degree of trauma which interpret into electrical signal that used to determine if trauma is serious or not based on predetermined threshold. This trauma can be occuard due to any kind of accidents. So, this paper established a detection system to request instant help from emergency department and relatives by delivering them an SMS contains the latitude and longitude. In usual mode helmet can operate as tracking tool monitored by the relatives.]]>
<![CDATA[Design and development of a parallelized algorithm for face recognition in mobile cloud environment ]]>
<![CDATA[K. N. Bhatt]]>;
<![CDATA[Sanket S Naik Dessai]]>;
<![CDATA[V. S. Yerragudi]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp47-55
<![CDATA[Face recognition is the biometric application to recognise the identity. Face recognition application holds a set of images which are called databases stored by the user at cloud database. Cloud computing environment, database can be stored in the cloud environment to achieve huge data storage area. The problem with these data storages are that because of that huge size processing on this storage takes too much of compiling time. This paper aims to develop face recognition in mobile cloud environment by exploiting data or task parallelism in existing face recognition algorithms. To design and develop parallel PCA based face recognition algorithm. The parallel PCA face recognition algorithm has been deployed in the cloud server for performing PCA by request of user. It matches the image on the cloud server and gives response back to the user in the fewer amounts of time and with reduced latency. The developed Parallel PCA face recognition algorithm has minimized the overall response time for the face recognition algorithm. The performance of the developed system is tested and analysed on real face images. To analyse the developed system, a centralized and distributed based server methods are developed and comparison is being carried out. The conclusion drawn that the distributed server improves the efficiency as well as the computing power as compared with centralized server system. The comparison of centralized and distributed based servers is carried out by observing the time taken while varying the number of images in the training dataset.]]>
<![CDATA[Cost-efficient reconfigurable geometrical bus interconnection system for many-core platforms ]]>
<![CDATA[Tirumale Ramesh]]>;
<![CDATA[Khalid Abed]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp77-89
<![CDATA[System-on-chip (SoC) embedded computing platforms can support a wide range of next generation embedded artificial intelligence and other computationally intensive applications. These platforms require cost effective interconnection network. Network-on-chip has been widely used today for on-chip interconnection. However, it is still considered expensive for large system sizes. As full bus-based interconnection has high number of bus connections, reduced bus connections might offer considerable implementation economies with relatively small design cost for field programmable gate arrays (FPGAs) based embedded platforms. In this paper, we propose a cost efficient generalized reconfigurable bus-based interconnection for many-core system with reduced number of bus connections. We generalize the system with b =min {n,m}/k number of interconnect buses in which where n is the number of processor cores, m is the number of memory-modules and k is the general bus reduction factor. We present four geometrical interconnect configurations and provide their characterization in terms of memory bandwidth, cost per bandwidth and bus fault tolerance for various system sizes. Our results show that these configurations provide reduced cost per bandwidth and can achieve higher system throughput with bus cache.]]>
<![CDATA[Digital brain: Model-based framework for dependable electroencephalogram sensing and actuation in internet of things system ]]>
<![CDATA[R. J. Kavitha]]>;
<![CDATA[Saravanan K. K.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp168-175
<![CDATA[Real-time brain internet of thing (IoT) frameworks are expensive. But, creating a cheaper framework has been quickened incredibly by the superior investigation that's being done on virtual brain. The passing of an imperative individual on a mystery mission is considered delicate data and must be taken care of with as much security as conceivable. By guaranteeing this discreteness, the time taken for the message of their passing to reach the pertinent specialist is expanded to up to a few days. The time taken to provide the message is as well. These days, the advancements in equipment expanding the capacities of the virtual brain and of the wearable brain IoT sensors have made the advancement of various unused program systems conceivable for engineers to make valuable applications that combine the human brain with IoT. Different tactile pathways are too empowered for communications of the human brain with bigger measured data. The fundamental point of this extend is to transfer secret records onto the clouds safely.]]>
<![CDATA[Obstacle Avoiding Robot Car ]]>
<![CDATA[Thakkar, Jayati Anilkumar]]>;
<![CDATA[Shah, Trusha]]>;
<![CDATA[Shaikh, Nishat]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp%p
<![CDATA[This paper proposes a design and implementation of a remote-controlled car run by Bluetooth Technology via an Android device. In this work, hardware and software technologies are used such as Arduino, Motor driver and Bluetooth module. Arduino is an Opensource prototyping platform supported easy-to-use hardware and software. Arduino uses an ATmega328 microcontroller. The objective of this project is to form an omnipresent technology for automobiles that operate in lifestyle with an effective system. In this project, the brain of the robot, Arduino microcontroller is programmed in such a way that it can detect any obstacle in a defined range and can choose a path with no obstacle in between. Since robotics has become a significant part in our standard of living and also within the engineering field and it plays an important role within the development of latest technology, This project can be made in a very bigger scale for real-time vehicles.This paper proposes a design and implementation of a remote-controlled car run by Bluetooth Technology via an Android device. In this work, hardware and software technologies are used such as Arduino, Motor driver and Bluetooth module. Arduino is an Opensource prototyping platform supported easy-to-use hardware and software. Arduino uses an ATmega328 microcontroller. The objective of this project is to form an omnipresent technology for automobiles that operate in lifestyle with an effective system. In this project, the brain of the robot, Arduino microcontroller is programmed in such a way that it can detect any obstacle in a defined range and can choose a path with no obstacle in between. Since robotics has become a significant part in our standard of living and also within the engineering field and it plays an important role within the development of latest technology, This project can be made in a very bigger scale for real-time vehicles.]]>
<![CDATA[Implementation of video surveillance system using embedded Blackfin processor ]]>
<![CDATA[Sanket Dessai]]>;
<![CDATA[Deepa Kannan]]>;
<![CDATA[Shiva Prasa Yadav]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp115-122
<![CDATA[The video surveillance is critical system to track the people at the various places and to track and monitor the nuciencess bound to be happened. On the other side several studies have proved and showed the hit and miss nature of human intervention to spot change in a surrounding environment which increasing the designer challenges for the development of video surveillance system with the help of embedded processor. The designer faces a greater challenge to apply the principle of embedded systems and develop the system smart features with low power and cost for the required applications of VSS. System requirement specification (SRS), Hardware design document (HDD), Software design document and test procedure has been arrived and developed to achieve VSS system. Blackfin processor has high end video engines and is more suitable for development of video surveillance system (VSS). The VSS is designed and developed using ADSP BF533 Ez-kit lite board. Peripheral like parallel peripheral interface (PPI) is used to interface between camera and processor. Also, it is used for interfacing processor and TV. The master-slave communication is established between two Blackfin processors through SPORT to transfer the captured frame from camera to display on TV. Power management is also implemented to save the power of the system.]]>
