International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
456 Documents
<![CDATA[An internet of things belief rule base smart system to predict earthquake ]]>
<![CDATA[Md. Mahashin Mia]]>;
<![CDATA[Abdullah Al Hasan]]>;
<![CDATA[Rahman Atiqur]]>;
<![CDATA[Rashed Mustafa]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp149-156
<![CDATA[An intelligent belief rule base (BRB) based system with internet of things (IoT) integration can evaluate earthquake prediction (EP). This ingenious and rational system can predict earthquake by aggregating changed animal behavior combined with environmental and chemical changes which are taken as real time inputs from sensors. The BRB expert system blends knowledge demonstration criterion like attribute weight, rule weight, belief degree. The intelligent BRB system with IoT predicts the probable occurrence of the earthquake in a region based on the sign and symptoms culled by the persistent sensors. The final result taken from Intelligent BRB system with IoT integration is compared with expert and fuzzy-based system. The projected method gives a better prediction than the up-to-date expert system and fuzzy system]]>
<![CDATA[Comparing reliabilities of centralized and distributed switching architectures for reconfigurable 2D arrays ]]>
<![CDATA[Behrooz Parham]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp123-129
<![CDATA[Whether used as main processing engines or as special-purpose adjuncts, processor arrays are capable of boosting performance for a variety of computation-intensive applications. For large processor arrays, needed to achieve the required performance level in the age of big data, processor malfunctions, resulting in loss of computational capabilities, form a primary concern. There is no shortage of alternative reconfiguration architectures and associated algorithms for building robust processor arrays. However, a commensurately extensive body of knowledge about the reliability modeling aspects of such arrays is lacking. We study differences between 2D arrays with centralized and distributed switching, pointing out the advantages of the latter in terms of reliability, regularity, modularity, and VLSI realizability. Notions of reliability inversion (modeling uncertainties that might lead us to choose a less-reliable system over one with higher reliability) and modelability (system property that makes the derivation of tight reliability bounds possible, thus making reliability inversion much less likely) follow as important byproducts of our study.]]>
<![CDATA[Neural net implementation of steam properties on FPGA ]]>
<![CDATA[R. V. S. Krishna Dutt]]>;
<![CDATA[R. Ganesh]]>;
<![CDATA[P. Premchand]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp186-194
<![CDATA[Real time applications like model predictive control, monitoring and data reconciliation of power plants and industrial processes employ nonlinear mathematical models and require thermodynamic properties and their derivatives of working fluids. Applications like super heater temperature control based on energy balance and real time data reconciliation, require an efficient and a compact method for simultaneous estimation of thermodynamic properties, and their partial derivatives suitable for implementation in field-programmable gate array (FPGA). However, the complex mathematical formulations of these properties prohibit direct implementations in FPGAs. Single artificial neural network (ANN) architecture is used to replace the entire code in higher level languages, running into a few thousand lines. FPGA implementation of a compact neural network for the entire range of thermodynamic properties is presented. Large arguments in sigmoid function are factored into a product of integer and a fractional part which is represented using series approximation with five terms only and the integers are represented in look up table (LUT). This ensures optimum storage and computational burden for the above applications. The ANN is implemented in IEEE 754 floating point with synthesis in Xilinx ISE design suite using Verilog HDL. The results are presented for a typical pressure versus saturation temperature.]]>
<![CDATA[Effect of integrated power and clock networks on combinational circuits ]]>
<![CDATA[Rajeshwari Bhat]]>;
<![CDATA[Mohammad Rashid Ansari]]>;
<![CDATA[Ruqaiya Khanam]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i3.pp242-248
<![CDATA[Reduction of power consumption is necessary in a system on chip. To achieve this, power and clock networks can be integrated. This leads to a significant reduction in power consumption in a circuit. This paper explores the effect of such a network on various combinational circuits and compares the power consumption of these circuits with conventional combinational circuits. The combinational circuits which are powered by the proposed circuit consume lesser power as compared to conventional combinational circuits.]]>
<![CDATA[Efficient adaptation of the Karatsuba algorithm for implementing on FPGA very large scale multipliers for cryptographic algorithms ]]>
<![CDATA[Walder Andre]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i3.pp235-241
<![CDATA[Here, we present a modified version of the Karatsuba algorithm to facilitate the FPGA-based implementation of three signed multipliers: 32-bit × 32-bit, 128-bit x 128-bit, and 512-bit × 512-bit. We also implement the conventional 32-bit × 32-bit multiplier for comparative purposes. The Karatsuba algorithm is preferable for multiplications with very large operands such as 64-bit × 64-bit, 128-bit × 128-bit, 256-bit × 256-bit, 512-bit × 512-bit multipliers and up. Experimental results show that the Karatsuba multiplier uses less hardware in the FPGA compared to the conventional multiplier. The Xilinx xc7k325tfbg900 FPGA using the Genesis 2 development board is used to implement the proposed scheme. The results obtained are promising for applications that require rapid implementation and reconfiguration of cryptographic algorithms. Here, we present a modified version of the Karatsuba algorithm to facilitate the FPGA-based implementation of three signed multipliers: 32-bit × 32-bit, 128-bit x 128-bit, and 512-bit × 512-bit. We also implement the conventional 32-bit × 32-bit multiplier for comparative purposes. The Karatsuba algorithm is preferable for multiplications with very large operands such as 64-bit × 64-bit, 128-bit × 128-bit, 256-bit × 256-bit, 512-bit × 512-bit multipliers and up. Experimental results show that the Karatsuba multiplier uses less hardware in the FPGA compared to the conventional multiplier. The Xilinx xc7k325tfbg900 FPGA using the Genesis 2 development board is used to implement the proposed scheme. The results obtained are promising for applications that require rapid implementation and reconfiguration of cryptographic algorithms.]]>
<![CDATA[Long Term Evolution Band Selectable Digital up Converter ]]>
<![CDATA[Gowda, Nayana]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp%p
<![CDATA[Wireless base-station Radio consists of many important blocks like Digital Front end (DFE), Digital to analog converters(DAC) , Analog to Digital converter(ADC) and many analog amplifiers to transmit and receive the required RF signals. DFE blocks helps in easy configuration of the carriers within the spectrum available. Performance of a Radio mainly depends on the better implementation of the DFE. The output of the Base band signals are fed to the DFE block which implements the required changes to the input signal and feeds the data to a higher sample rate DAC for downlink, this process of up sampling of data is done by Digital Up convertor (DUC) block which is a part of the DFE. Similarly the DFE takes processed digital converted data from the ADC and down converts the signal to the baseband sample rate for further processing. This Process of down sampling of data is done by Digital down convertor (DDC) block which also is a part of the DFE. The number of antenna ports and the number of carrier required to configure per antenna port defines the requirement of for the Number of DUC & DDC paths to be used in the DFE design. If there are 4 antenna ports and single carrier configuration per antenna port then the number of DUC block required will be 4 for this design. Hence the effective implementation of the DUC/DDC block will define the effective resource requirement for a DFE design.]]>
<![CDATA[Recurrence relation and DNA sequence: A state-of-art technique for secret sharing ]]>
<![CDATA[Anirban Bhowmik]]>;
<![CDATA[Sunil Karforma]]>;
<![CDATA[Joydeep Dey]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i1.pp65-76
<![CDATA[During the transmission over the Internet, protection of data and information is an important issue. Efficient cryptographic techniques are used for protection but everything depends on the encryption key and robustness of encryption algorithm. Threshold cryptography provides the development of reliable and strong encryption and key management machine which can reconstruct the message even in the case of destruction of some particular numbers of shares and at the opposite the data cannot be reconstructed unless an allowable set of shares are been gathered. The earlier techniques available in literature result in high computational complexity in the course of both sharing and reconstructing of message. Our method employs a brand new easy protecting technique based totally on unit matrix. The simple AND operation is used for percentage generation and reconstruction can be finished by way of easy ORing the stocks with threshold cost. We are proposing a sharing approach in conjunction with conventional cryptography technique for key control to make the key greater sturdy and for encryption we have used a session key the use of the idea of recurrence relation and DNA series Different types of experimental results confirm authenticity, confidentiality, integrity and acceptance of our technique.]]>
<![CDATA[Co-simulation of linear congruential generator by using Xilinx system generator and MATLAB Simulink ]]>
<![CDATA[Suneeta Suneeta]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp109-114
<![CDATA[Arbitrary numerals are utilized in a wide range of uses. Genuine arbitrary numeral generators are moderate and costly for some applications while pseudo arbitrary numeral generators (RNG) do the trick for most applications. This paper fundamentally concentrates around the co-simulation of the linear congruential generator (LCG) model utilizing the Xilinx System generator and checking on Matlab Simulink. The design is obtained from the LCG calculation offered by Lehmer. Word lengths decrease strategy has been utilized to streamline the circuit. Simulation has been done effectively. The effective N bit LCG is structured and tried by utilizing demonstrating in MatLab Simulink. The Co-simulation of the model is done by utilizing the Xilinx system generator. This paper conducts an exhaustive search for the best arbitrary numeral generator in a full period linear congruential generator (LCG) with the largest prime numbers.]]>
<![CDATA[Processor performance metrics analysis and implementation for MIPS using an open source OS ]]>
<![CDATA[Varuna Eswer]]>;
<![CDATA[Sanket Dessai]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i2.pp137-148
<![CDATA[Processor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varying load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction execution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twentyseven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analyzing architectural issues, system benchmarking, scalability, address space analysis, studies of bus communication among processor and its workload sharing characterization and kernel profiling.]]>
<![CDATA[Image processing using a reconfigurable platform: Pre-processing block hardware architecture ]]>
<![CDATA[Chiranjeevi G. N.]]>;
<![CDATA[Subhash Kulkarni]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 3: November 2021 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v10.i3.pp230-236
<![CDATA[Real time image processing is a challenging task in which fetching the sub image requires offset memory access apart from core processing needs. This paper aims at overcoming the offset needs for memory addressing in pre-processing blocks. Another feature of this present work is to appending the image data with customized algorithmic reequipments viz duplicating, zero padding. For KxK kernel size, the proposed hardware architecture can be programmed to fetch K pixels in one cycle, reducing the data access time. Results have been compared with software-based processing for KxK spatial filtering. performance indicates significant timing improvement using proposed pre-processing hardware block.]]>
