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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 456 Documents
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Machine to machine communication enabled internet of things: a review Rajagopal Sudarmani; Kanagaraj Venusamy; Sathish Sivaraman; Poongodi Jayaraman; Kannadhasan Suriyan; Manjunathan Alagarsamy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp126-134

Abstract

Internet of things (IoT) will be the main part in upcoming generation devices that would not simply sense and report, also will have the controlling capability. It may be a connected vehicle, connected devices, robot, a building automation system, a door lock or a thermostat, these connected machines or devices will provide greater impact on our daily lives. Control data and the operating instructions could be protected to ensure control and autonomy for our safety and security, this could be a critical task. Privacy and security are important consideration in designing the system. With the intense growth of devices or devices with facilities such as computing and communication are carried out using a profound technology known as machine to machine (M2M) communication, which is specially designed for cross‐platform integration. In many industries, smart homes, smart cities, smart agriculture, government, connected devices, security, healthcare, education, public safety, and supply chain management. Internet of things (IoT) and machine to machine communication have to be implemented in near future. Also, this paper gives an in depth view about the different M2M techniques with interconnected IoT for truly connected, smart, and sustainable world.
IoT based E-vehicle monitoring system using sensors and imaging processing algorithm Manjunathan Alagarsamy; Prabakaran Kasinathan; Geethalakshmi Manickam; Prabu Ragavendiran Duruvarajan; Jeevitha Sakkarai; Kannadhasan Suriyan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp196-204

Abstract

Human evolution has included the development of transportation systems. People are currently driving a significant number of fuel-powered automobiles. This resulted in an increase in the number of accidents as well as pollution in the environment. To address the disadvantages of gasolinebased vehicles, this study presents an IoT-based E-vehicle monitoring system (E-VMS) for early accident detection and to make the environment cleaner and greener by using alternative energy. E-VMS employs internet of things (IoT) technology to continuously monitor the vehicle as well as to access and control it remotely. The IoT devices installed in vehicles are built using an Arduino microcontroller and sensors to detect accidents quickly. When an accident occurs, the E-VMS recognizes it quickly and determines the severity of the incident. The machine will then promptly alert the authorities. The E-VMS is also familiar with the GPS system. This will allow the E-VMS to maintain track of the cars' location in real time. This information will be used to locate the car in the event of an accident or theft. The E-VMS system's results were promising in terms of accurately identifying accidents, determining the severity of the accident, and determining the position of the vehicle.
Pre-current amplifier based transimpedance amplifier for biosensors Jyoti M. Roogi; Manju Devi
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp188-195

Abstract

In this paper, we present current amplifier based transimpedance amplifier (TIA) for biosensor applications. Proposed design has low-noise, high Transimpedance gain that can be used for low current measurement applications. The current amplifier based TIA is implemented in order to resolve the fabrication issues related to high value feedback resistor. In this design, the input block to TIA is a low amplitude current amplifier. The designed amplifier is implemented in 90 nm complementary metal-oxide semiconductor (CMOS) technology. The design achieves transimpedance gain of 800 kΩ with a bandwidth of 5 kHz and input referred current noise is of 0.152 pA/√???????? for an input of 41 nA bypassed from current amplifier with input of 200 pA.
A laboratory scale IoT-based measuring of the solar photovoltaic parameters Arsyad Cahya Subrata; Tole Sutikno; Sunardi Sunardi; Anggit Pamungkas; Watra Arsadiando; Ahmad Raditya Cahya Baswara
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp135-145

Abstract

Harvesting solar energy as a renewable energy source has received significant attention through serious studies that could be applied massively. However, the nonlinear nature of photovoltaic (PV) concerning the surrounding environment, especially irradiation and temperature, affects the resulting output. Therefore, the correlation between environmental parameters and PV's energy needs to be studied. This paper presents a design for measuring solar PV parameters monitored on a laboratory scale. The monitoring is based on internet of things (IoT) technology analyzed in realtime. The system was tested in various weather conditions for 18 hours. The results obtained indicate that the output voltage was influenced by the lighting factor of the PV and the surrounding temperature.
CEAZA mega board: an open-source data logger for scientists Adrian Gallardo; Cristian Orrego Nelson; Shelley MacDonell
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp175-187

Abstract

Over the last decade many researchers have taken advantage of the technology boom related to the launch of the Arduino platform to make their own datalogging devices. Many of these developments ended with the first functional prototypes in which multiple electronic boards are mixed by wiring/soldering and then used in datalogging activities. In this study we present a new, simple, robust, and expandable datalogger board based on maker’s community integrations. Our datalogger board extends previous work in this area as we designed an Arduino Mega 2560 derivative integrated board that is compatible with existing developments but was also designed and implemented considering requirements such as low power consumption, expandability, and integration. Different tests were made so reliability in low temperatures and low energy needs are satisfied. Is expected that the scientific community can add this board to their tool set, as this board solves the energy problem and present an easy transition from handmade logger integrations.
Comparison of breast cancer classification models on Wisconsin dataset Rania R. Kadhim; Mohammed Y. Kamil
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp166-174

Abstract

Breast cancer is the leading cause of death for women worldwide. Cancer can be discovered early, lowering the rate of death. Machine learning techniques are a hot field of research, and they have been shown to be helpful in cancer prediction and early detection. The primary purpose of this research is to identify which machine learning algorithms are the most successful in predicting and diagnosing breast cancer, according to five criteria: specificity, sensitivity, precision, accuracy, and F1 score. The project is finished in the Anaconda environment, which uses Python's NumPy and SciPy numerical and scientific libraries as well as matplotlib and Pandas. In this study, the Wisconsin diagnostic breast cancer dataset was used to evaluate eleven machine learning classifiers: decision tree, quadratic discriminant analysis, AdaBoost, Bagging meta estimator, Extra randomized trees, Gaussian process classifier, Ridge, Gaussian nave Bayes, k-Nearest neighbors, multilayer perceptron, and support vector classifier. During performance analysis, extremely randomized trees outperformed all other classifiers with an F1-score of 96.77% after data collection and data analysis.
Design and performance analysis of efficient hybrid mode multi-ported memory modules on FPGA platform Druva Kumar Siddaraju; Roopa Munibyrappa
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp115-125

Abstract

The multi-ported memories (MPMs) are essential and are part of the parallel computing system for high-performance features. The MPMs are commonly used in most processors and advanced system-on-chip (SoC) for faster computation and high-speed processing. In this manuscript, efficient MPMs are designed using the integration of hierarchical bank division with xor (HBDX) and bank division with remap table (BDRT) approaches. The BDRT approach is configured using remap table with a hash write controlling mechanism to avoid write conflicts. The different multiple read ports are designed using BDX, and HBDX approaches are discussed in detail. The results of 2W4R and 3W4R memory modules are analyzed in detail concerning chip area, operating frequency (MHz), block random access memories (BRAMs), and throughput (Gbps) for different memory depths on virtex-7 field programmable gate array (FPGA). The 2W4R utilizes 2.27% slices, operates at 268 MHz frequency by consuming 64 BRAMs for 16K memory depth. Similarly, the 3W4R uses 2.28% slices, operates at 250 MHz frequency by consuming 96 BRAMs for 16K Memory depth. The proposed designs are compared with existing MPM approaches with better chip utilization (Slices), frequency, and BRAMs on the same FPGA device.
Automatic generation of user-defined test algorithm description file for memory BIST implementation Aiman Zakwan Jidin; Razaidi Hussin; Lee Weng Fook; Mohd Syafiq Mispan; Loh Wan Ying
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp103-114

Abstract

Memory built-in self-test (BIST) is a widely used technique to allow the self-test and self-checking of the embedded memories on chips after the fabrication process. It can be used by implementing a standard testing algorithm available in the EDA tool library or a user-defined algorithm (UDA). This paper presents the development of software that automatically generates a description file of a UDA to be deployed for memory BIST circuit implementation using Tessent memory BIST software. It comprises the test setup and also the microprogram coding for each instruction to be executed when performing tests on embedded memories. The proposed automation software was tested by using March SR as the input algorithm and the results obtained from the simulations show that the output test patterns generated by the implemented memory BIST match the expected patterns and passed all the tests, which validated the correct functionality of the UDA description file generation. The proposed automation software also fast generation the UDA description file, which was completed in less than 500 ms.
Successive cancellation decoding of polar codes using new hybrid processing element Sujanth Roy James; Lakshminarayanan Gopalakrishnan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp157-165

Abstract

Polar codes are one of the best linear block codes that are capacity achieving and incorporating along with it a simplified encoding and decoding routines. Successive cancellation (SC) algorithm is one of the predominantly used decoding algorithms due to its low complexity. It has broad scopes for hardware architecture design and reformulation. For polar code, the trade-off among the long latency and the silicon area of the SC algorithm is a bottleneck for the design of a high throughput polar decoder. The available prior SC polar decoder designs have higher area requirements for higher block length. This paper introduces a unique reformulation of the processing element (PE) block of SC decoding. The proposed reformulation leads to two benefits: firstly, critical path and hardware complexity of the PE are meaningfully reduced by using a unified adder block. Secondly, the silicon area requirement and the power consumption were also reduced considerably without any loss in performance. The proposed PE is used to build the decoder for various block lengths. Moreover, a Gate-level analysis of the proposed decoder has revealed that the design attains an 18% area reduction and 38% reduction in power consumption over the conventional one with similar performance.
Design of wideband antenna using interdigital capacitance Kannadhasan Suriyan; Kanagaraj Venusamy; Indira Priya Ponnuvel; Syed Khaja Ahmedudin Zakir; Manjunathan Alagarsamy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 1: March 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i1.pp149-156

Abstract

A pair of wideband antenna serve as an impedance transformer for the proposed antenna, which consists of a dipole with periodic capacitive loading. Periodic capacitive loading is achieved at each sector by adding interlaced coupling lines. In order to create a broad impedance bandwidth, the periodic interlaced coupling lines split each arm of the dipole into five portions. Currents are dispersed on the various sections at different frequencies. The suggested antenna is an excellent choice for radar applications since it has a high gain and a low amount of cross polarisation. With the aid of innovative design methods including codirectional inclusion of interdigital capacitance, this research study proposes an interdigital capacitance for wideband (WB) applications interdigital capacitor (IDC). The suggested IDC antenna, which works between 4.70 and 11 GHz, has dimensions of 6.36x6.35x1.6 mm3. This page explores in-depth data on gain over frequency, far field patterns, and surface current distribution on antennas. The suggested antenna's feasibility is shown by simulation data that demonstrates excellent equality on return loss.

Page 24 of 46 | Total Record : 456

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