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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 456 Documents
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Blockchain-based decentralized voting system with SHA-256 algorithm and facial recognition Kalyani, BJD; Modadugu, Jaya Krishna; Neelima, Sarabu
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp481-489

Abstract

Blockchain technology has completely changed the way data is stored and transactions are verified. It provides a dependable, transparent, and safe medium for communication and transaction validation. In order to solve the drawbacks of conventional electronic voting systems, the goal of this research project is to design a decentralized voting system based on blockchain technology. The suggested method offers an immutable and safe way to record and validate votes by utilizing the security and transparency capabilities of blockchain technology. The suggested approach provides an immutable and safe way to record and validate votes by utilizing the security and transparency capabilities of blockchain technology. This paper aims to provide a comprehensive process for digital identity authentication, create a voter interface that is compatible with Ethereum wallets, and apply smart contracts on the Ethereum network to speed up voter registration, ballot preparation, voting, and result tabulation. Additionally, this paper proposes to build up a multi-factor authentication system for election managers and validators to offer them safe and approved power over the voting process. By carefully examining the existing methods, this research highlights the flaws and weaknesses of traditional electronic voting systems and stresses the need for more trustworthy and secure voting technology. The proposed blockchain-based voting system offers an innovative solution to problems with voter fraud and election manipulation because of its irreversible blockchain record, which gives a high degree of transparency and integrity.
Enhancing scalability and efficiency in technological transaction utilizing dual-layer blockchain approach Kanimozhi, T.; Inbavalli, M.
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp452-462

Abstract

The leather industry encounters significant challenges in integrating blockchain technology and smart contracts into its complex supply networks. Despite technological advancements, existing supply chain management systems suffer from inefficiencies, opacity, and vulnerabilities to fraud. Blockchain offers promising solutions such as immutable ledgers, decentralized governance, and smart contract automation. However, scalability limitations hinder the efficient handling of high transaction volumes, impacting procurement, production, inventory management, and distribution processes, leading to delays and increased costs. This research aims to address these challenges by exploring innovative approaches, including dual-layer blockchain architectures incorporating sharding and state channels, tailored to the unique needs of the leather industry. By overcoming scalability barriers, the research seeks to unlock the transformative potential of blockchain technology and smart contracts, enhancing transparency, traceability, and efficiency in leather supply chains while ensuring global interoperability and regulatory compliance. Through empirical validation and comparative analysis, this study provides understandings into the practical implementation of blockchain solutions within the leather industry, offering strategic guidance for sustainable supply chain management practices.
Pipelined reconfigurable architecture for 5G software-defined radio systems Chalampalem, Vijaya Bhaskar; Pidugu, Munaswamy; Nagaraju, Sanacarapu
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp320-327

Abstract

The filters are used to allow a specific band of frequencies. In a wireless communication, the filter is used to select the frequency of operation with a narrow or broad band. As the generations increase the amount of data handled increases drastically. 5G data rate can be significantly deliver up to 20 Gigabits per second while 4G communication data rate is handled in the order of 100 Megabits per second. Now the challenge becomes processing data at such a speed with low power and low area specifications. The filters that can configure themselves as per the data received are reconfigurable filters so that the bandwidth is saved. Also, when the pipelining is introduced, the reconfigurable filter improves the performance of the design. This paper details about the pipelined reconfigurable finite impulse response (RFIR) filter with the simplest algorithm with auto updating capability. The design is modelled in Verilog hardware description language (HDL) language, synthesized for Cyclone III field-programmable gate array (FPGA). The results prove that the proposed filter increases only slightly with respect to delay and power dissipation with a trade off in area and maximum possible clock frequency.
Exploring the landscape of approximate subtraction methods in ASIC platform Priyadharshni, M.; Thinakaran, Rajermani; Naga Jyothi, Grande; Varadarajan, Vijayakumar; Murthy, C. Srinivasa
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp388-397

Abstract

Approximate computing has emerged as a crucial technique in modern computing, offering significant benefits for error-resilient applications. Error resilient applications include signal, image, audio processing, and multimedia. These applications will accept the errored results with some degree of tolerance. This approach allows these applications to process and embrace data that may deviate slightly from perfect accuracy. The utility of approximate computing extends to both hardware and software domains. In hardware, arithmetic units are particularly important, among that approximate subtractors have gained attention for their role in these units. A comparative study was conducted on various approximate subtractors from existing literature, considering structural analysis in all scenarios. These approximate subtractors are coded in Verilog hardware description language (HDL) and synthesized in Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65 nm technology. Out of the available choices, approximate subtractor 3 is particularly well-suited for processing higher bit data due to its reduced hardware complexity and minimal error. Notably, it outperforms exact subtractors by achieving a notable reduction of 20% in the area delay product (ADP) and 15% in the power delay product (PDP) as process innovation. These improvements highlight the efficiency and effectiveness of approximate subtractor 3, making it a compelling option for various computing applications which accept the inaccurate results.
Investigating the performance of RNN model to forecast the electricity power consumption in Guangzhou China Mingying, Han; Ab Malik, Azman; Allias, Noormadinah; Hamzah, Irni Hamiza binti
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp497-506

Abstract

The project initiatives to create a reliable prediction model for power loads in Guangzhou, China. The power industry is facing issues due to rapid market growth and the necessity for better grid management, prompting this response. In developing the models, conventional machine learning models have been used so far, but in this study, the performance of deep learning is investigated. Therefore, the recurrent neural network (RNN) was selected for the prediction of electricity consumption. Later, the performance of the model was compared with autoregressive integrated moving average (ARIMA), long short-term memory (LSTM), and RNN. The experimental results show that the RNN outperforms ARIMA and LSTM, with an R² value of 0.92, an RMSE of 0.13107 and an MAE of 0.0176. The project improved power resource planning and management, selected an acceptable forecasting model RNN and contributed to forecasting technology developments. The study identified limits in historical data availability and quality, as well as external influences affecting the studies. RNN models can help optimize resource allocation and improve energy planning.
Design of a dual-band bandpass filter with shunt stubs for wireless local area network and satellite communication system Abraham, Jacob; Suriyan, Kannadhasan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp490-496

Abstract

High-performance radio frequency (RF) modules are required in transmitter and reception devices due to the recent expansion of wireless technology. The power amplifier, low-noise amplifier, filter, and mixer are the most crucial components in the RF transmitter/receiver chain. This work presents the design and analysis of a dual-band bandpass filter (BPF) for wireless local area network (WLAN) and C-band satellite applications. Stubs of the proper electrical length that are open and short-circuited are used to implement the filter. The low pass performance is generated by the open-circuited stubs. Short-circuited stubs achieve high-pass performance, while the combination of open and short-circuited stubs achieves bandpass performance. We confirm the filter's behaviour using the advanced design system 2022 simulation tool. The findings of return loss and insertion loss confirm the simulation-level performance analysis of the filter. The result demonstrates the suggested BPF's dual-band behaviour at 4 GHz and 6 GHz.
Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications Venkata Sudhakar, Chowdam; Potladurty, Suresh Babu; Karipireddy, Prasad Reddy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp398-411

Abstract

The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this paper, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HA) and full adders (A-FA), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the ripple carry adder (RCA), carry save adder (CSA), conditional sum adder (COSA), carry select adder (CSLA), and clock gating technique. The proposed multipliers are implemented in Verilog hardware description language (HDL) and simulated on the Xilinx VIVADO 2021.2 design tool with target platform Artix-7 AC701 FPGA. The simulation results found that unsigned and signed approximate multiplier power consumption was reduced by 13% and 18.18% respectively and enhanced accuracy.
Design and development of multiband multi-mode frequency reconfigurable CPW-fed antenna for 5G wireless communication Tiwari, Annu; Yilmaz, Muhammed Yasir; Soni, Gaurav Kumar; Yadav, Dinesh
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp328-338

Abstract

This research develops, simulates, fabricates and measured a coplanar waveguide (CPW)-fed multiband multi-mode frequency reconfigurable antenna for 5G wireless communication. The antenna is design on Rogers RT5880 substrate with a dielectric constant of 2.2, a thickness of 0.508 mm, and a loss tangent (tanδ) of 0.0009 and the dimension is 30×28×0.508 mm3. The presented antenna has shown good impedance matching with reflection coefficients ranging from -14.82 to -50.36 dB at different frequencies between 6 GHz to 24 GHz. The presented frequency reconfigurable antenna design includes four PIN diodes, resistors, and inductors, enabling 16 different configurations. The simulated outcomes showed varied S parameter values and gains, demonstrating the antenna's flexibility. Measurements were taken using vector network analyzer (VNA) and anechoic chamber to assess reflection coefficient (|S11|) and gain, confirming the antenna's performance. The antenna's ability to reconfigure dynamically without losing signal integrity makes it suitable for 5G wireless applications. It meets and exceeds the requirements for multiband operation, validated by comprehensive simulations and measurements, showing its potential for wide use.
Classifying IoT firmware security threats using image analysis and deep learning Rouagubi, Abdelkabir; El Youssofi, Chaymae; Chougdali, Khalid
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp546-557

Abstract

As the internet of things (IoT) grows, its embedded devices face increasing vulnerability to firmware-based attacks. The lack of robust security mechanisms in IoT devices makes them susceptible to malicious firmware updates, potentially compromising entire networks. This study addresses the classification of IoT firmware security threats using deep learning and image-based analysis techniques. A publicly available dataset of 32×32 grayscale images, derived from IoT firmware samples and categorized as benignware, hackware, and malware, was utilized. The grayscale images were converted into three-channel RGB format to ensure compatibility with convolutional neural networks (CNNs). We tested multiple pre-trained CNN architectures, including SqueezeNet, ShuffleNet, MobileNet, Xception, and ResNet50, employing transfer learning to adapt the models for this classification task. Both ResNet50 and ShuffleNet achieved exceptional performance, with 100% accuracy, precision, recall, and F1-score. These results validate the effectiveness of our methodology in leveraging transfer learning for IoT firmware classification while maintaining computational efficiency, making it suitable for deployment in resource-constrained IoT environments. T
Test and measurement automation of printed circuit board assembly using digital oscilloscope Kumar, Sanjeev; Prasad, Deepak; Pandey, Manoj
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp463-471

Abstract

The testing and measurement (TM) of electrical parameters of printed circuit board assembly (PCBA) plays an integral part in the manufacturing sectors. These industries work on embedded system which widely use digital oscilloscopes (DO) for such purposes, however, operate them manually. An exponential rise in the implementation of industry 4.0 with the increasing demand for industrial products makes manual TM cumbersome. The automation of oscilloscopes (AO) remains a viable alternative to these issues requiring further investigation. An accurate and automated TM block facilitates efficient design, development, and assembly of a fully functional system hence addressed here. The AO has been carried out using generalized software that can be configured based on industry requirements. It subsequently stores the data on the server for better traceability. The automated software is developed using VB.NET and installed on a personal computer. Experiments reveal the proposed approach saves approximately 60%-70% of the time required for each PCBA operation than that of the manual system. This can enhance the productivity of the industry in terms of manpower and Resource utilization with a reduction in operating costs.

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