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All Journal International Journal of Electrical and Computer Engineering IAES International Journal of Artificial Intelligence (IJ-AI) Mechatronics, Electrical Power, and Vehicular Technology Jurnal INKOM Jurnal Simetris TELKOMNIKA (Telecommunication Computing Electronics and Control) Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics Journal of ICT Research and Applications Setrum : Sistem Kendali-Tenaga-elektronika-telekomunikasi-komputer ELINVO (Electronics, Informatics, and Vocational Education) JURNAL NASIONAL TEKNIK ELEKTRO Bulletin of Electrical Engineering and Informatics Proceeding of the Electrical Engineering Computer Science and Informatics International Journal of Supply Chain Management Indonesian Journal of Electrical Engineering and Computer Science Community Empowerment Jurnal Nasional Teknik Elektro dan Teknologi Informasi Jurnal Ilmiah Teknik Elektro Jurnal INFOTEL
Trio Adiono
Institut Teknologi Bandung
Arts Humanities Computer Science & IT Control & Systems Engineering Decision Sciences, Operations Research & Management Education Electrical & Electronics Engineering Energy Engineering Environmental Science Industrial & Manufacturing Engineering Public Health Social Sciences Transportation

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Journal : Journal of ICT Research and Applications

 1 
An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification Trio Adiono; Hans G. Kerkhoff; Hiroaki Kunieda
Journal of ICT Research and Applications Vol. 3 No. 1 (2009)
Publisher : LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/itbj.ict.2009.3.1.4

Abstract

This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which enables core verification at actual speed. It significantly decreases the verification time due to the large number of required test vectors in typical MPEG4 verification. Furthermore, it also makes the system scalable for functional core expansion due to upgrading of standards. The proposed infrastructural IP is also linked to PC-based interactive tools to simplify the verification of individual and integrated cores. It also provides detailed diagnostic data that enables simple system debugging. The debugging tools also feature test-pattern generation and simulation of expected values. Actual system implementation has shown full functionality of our proposed method.
A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm Rachmad Vidya Wicaksana Putra; Rella Mareta; Nurfitri Anbarsanti; Trio Adiono
Journal of ICT Research and Applications Vol. 6 No. 2 (2012)
Publisher : LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/itbj.ict.2012.6.2.3

Abstract

In  the  literature, several approaches  of  designing  a  DCT/IDCT-based image compression system have been proposed.  In this paper,  we present a new RTL design approach with as main  focus developing a  DCT/IDCT-based image compression  architecture  using  a  self-created  algorithm.  This  algorithm  can efficiently  minimize  the  amount  of  shifter -adders  to  substitute  multiplier s.  We call  this  new  algorithm  the  multiplication  from  Common  Binary  Expression (mCBE)  Algorithm. Besides this algorithm, we propose alternative quantization numbers,  which  can  be  implemented  simply  as  shifters  in  digital  hardware. Mostly, these numbers can retain a good compressed-image quality  compared to JPEG  recommendations.  These  ideas  lead  to  our  design  being  small  in  circuit area,  multiplierless,  and  low  in  complexity.  The  proposed  8-point  1D-DCT design  has  only  six  stages,  while  the  8-point  1D-IDCT  design  has  only  seven stages  (one  stage  being  defined as  equal  to  the  delay  of  one  shifter  or  2-input adder). By using the pipelining method, we can achieve a high-speed architecture with latency as    a  trade-off consideration. The  design has been synthesized and can reach a speed of up to 1.41ns critical path delay (709.22MHz). 
VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm Rachmad Vidya Wicaksana Putra; Trio Adiono
Journal of ICT Research and Applications Vol. 10 No. 1 (2016)
Publisher : LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/itbj.ict.res.appl.2016.10.1.5

Abstract

Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.
An Inter-Processor Communication (IPC) Data Sharing Architecture in Heterogeneous MPSoC for OFDMA Trio Adiono; Rian Ferdian; Febri Dawani; Imran Abdurrahman; Rachmad Vidya Wicaksana Putra; Nur Ahmadi
Journal of ICT Research and Applications Vol. 12 No. 1 (2018)
Publisher : LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/itbj.ict.res.appl.2018.12.1.5

Abstract

Multiprocessor system-on-chip (MPSoC) promises better data management for parallel processing than conventional SoC. This feature is very suitable for wireless communication systems. Better data processing management can reduce resource utilization and can potentially reduce power consumption as well. Hence, this research aimed to minimize the orthogonal frequency-division multiple access (OFDMA) processing hardware by proposing a new data sharing architecture on a heterogeneous MPSoC platform that incorporates inter-processor communication (IPC), multi-processor, multi-bus, multi-frequency and parallel processing design of the medium access controller (MAC) layer. This MPSoC was designed based on a RISC processor with an AMBA multi-bus system. To achieve high throughput, the proposed MPSoC runs at two different frequencies, 40 MHz and 80 MHz. The proposed system was implemented and verified using FPGA. The verification results showed that the proposed system can work in real-time with a maximum throughput of 11 MBps using a 40 MHz system clock. The proposed MPSoC is a promising solution to perform OFDMA processing on 4G and 5G technologies.
Co-Authors Abdurrahman, Imran Adang Suwandi Ahmad Adijarto, Waskita Adinugraha, Erick Aditia Rifai Aditya F. Ardyanto Afandi, Najma Khansa Alya Agung, Anton Toni Agung, Anton Toni Ahmad Zaky Ramdani Alfi, Feiza Angga Pradana Angga Pradana Angga Pradana Angga Pratama Putra Angga Pratama Putra Angga Pratama Putra Angga Pratama Putra Angga Pratama Putra, Angga Pratama Arwin Datumaya Wahyudi Sumari Bambang Riyanto Trilaksono Braham Lawas Lawu Catherine Olivia Sereati Dawani, Febri Erick Adinugraha Erwin Setiawan Erwin Setiawan Erwin Setiawan, Erwin Fadjar Rahino Triputra Fadjar Rahino Triputra, Fadjar Rahino Farkhad Ihsan Hariadi Fathany, Maulana Yusuf Guno, Yomi Hans G. Kerkhoff Hans Kasan Hans Kasan Hariadi, Farkhad Ihsan Haslina Arshad Hidayat, Asyaraf Hiroaki Kunieda Idham Hafizh Imran Abdurrahman Infall Syafalni Irfan Gani Purwanda Joko Suryana Kasan, Hans Khilda Afifah Leonardi Paris Hasugian Maulana Yusuf Fathany Maulana Yusuf Fathany Maulana Yusuf Fathany Mohamad Dahsyat Mohamad Dahsyat, Mohamad Muhammad Arif Sulaiman Muhammad Husni Santriaji Nur Afyfah Suwadi Nur Ahmadi Nur Ahmadi Nurfitri Anbarsanti Octaviany, Siti Vivi Pamungkas, Sandi Purwanda, Irfan Gani Rachmad Vidya Wicaksana Putra Rachmad Vidya Wicaksana Putra Rachmad Vidya Wicaksana Putra Rachmad Vidya Wicaksana Putra Rachmad Vidya Wicaksana Putra Rachmad Vidya Wicaksana Putra Rachmad Vidya Wicaksana Putra Rella Mareta Rianto Adhy Sasongko Rianto Adhy Sasongko, Rianto Adhy Rifai, Aditia Ruzzakiah Jenal Septian G. P. Putra Sinantya Feranti Anindya SINANTYA FERANTI ANINDYA, SINANTYA FERANTI Suksmandhira Harimurti Sulaiman, Muhammad Arif Syifaul Fuada Waskita Adijarto Yulian Aska Yulian Aska Yulian Aska Yulian Aska Yulian Aska, Yulian Zainal Rasyid Mahayuddin