Garuda - Garba Rujukan Digital

Article Per Year (5 Year)

All

International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
Website

Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 456 Documents

13 14 15 16 17

NOC Based Router Architecture Design Through Decoupled Resource Sharing Using CABHR Algorithm A. Kalimuthu; M. Karthikeyan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 2: July 2017
Publisher : Institute of Advanced Engineering and Science

A Network-on-Chips (NoCs) is rapid promising for an on-chip alternative designed in support of many-core System-on-Chips (SoCs). In spite of this, developing an increased overall performance low latency Network on chip using low area overhead has always been a new challenge. Network on Chips (NoCs) by using mesh and torus interconnection topologies have become widely used because of the easy construction. A torus structure is nearly the same as the mesh structure, however, has very slighter diameter. In this regard, we propose effective router design for Decoupled Resource sharing in a torus topology based on clustering algorithms Based Hierarchical Routing (CABHR) to get better the efficiency of NoC. We show that our approach is provides improved latency and energy consumption, overall performance developments compared to the most distinguished existing routing technique

Embedded Linux Based Shopping Assistance System Ayanabha Chakraborty; Prashant Konaje; Prabha Kasliwal
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 3: November 2013
Publisher : Institute of Advanced Engineering and Science

In a view to streamline shopping system and facilitate access to required commodities among innumerable varieties in a super market, personalized service can be exploited in automated manner through interactive graphical user interface. Implementation of location based several touch screen modules with a centralized database can provide easy, accurate and timely information in regards to query generated by the users. Availability of an item and its location with absolute identification are displayed on the screen to facilitate users to get access to it immediately. This not only saves valuable time and cumbersome manual procedure in finding desired products but also provides an easy-to-use interactive shopping experience without any effort. Personalized Shopping Assistance maintains a centralized database for all products in the super market with user-friendly graphical user interface touch screen modules at various locations.

A Power Efficient Self Biased OTA Design Based on g_m/I_D Methodology with Considering Load Variation, Temperature Variation and Power Supply Variation Vikas Mittal
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018
Publisher : Institute of Advanced Engineering and Science

The present work addresses the design of power efficient fully self biased OTA using a design methodology based on the transistor characteristics. This analog module was analyzed, designed and prototyped in TSMS 0.35μm CMOS technology. Simulation results are presented, in order to validate the methodology. The OTA has Gain of 41.35 dB and 3db bandwidth of 138.73 kHz and the UGB of 12.40MHz with the current consumption of 65.50 μA. The circuit does not have need of any DC external biasing circuit, only need to apply VDD (3.3 V). Here self biasing has been introduced with power consumption of 216.15μW. The results have been taken with load variations, temperature variations, and power supply variations. This circuit used in real time high frequency applications as in RF communication.

Development of Wireless Sensor Network for Traffic Monitoring Systems Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

Traffic congestion has been a major problem on roads around the world. In addition, there is increase in volume of traffic vehicle density at a steady rate. Thus traffic on major roads has to be controlled to keep the traffic flowing at an acceptable rate. Several schemes for replacing the predominantly used Round Robin (RR) scheme for reducing congestion at traffic junctions have been proposed. Dynamic traffic control schemes adapt to the changing traffic by monitoring the state (such as the number queued up on each lane.). These need appropriate sensing and monitoring systems. In this paper a traffic monitoring and control system based on AMR (Anistropic Magneto Resistive) vehicle sensors, wireless sensor network and a proiritised Weighted Round Robin (WRR) scheduling technique, is developed.AMR sensors installed in road pavement detect the number of vehicles waiting in a traffic lane. The AMR sensors are connected to the master controller to form a Zigbee based sensor network. The master node consists of an ARM processor integrated with a Zigbee masternode. The traffic control algorithm is implemented at master node which is responsible for taking traffic signaling decision. It receives sensor data from all the lanes. A two level priority algorithm with weighted round robin scheduling, where first and second maximum weighted lane are to pass the signal is developed, To avoid starving the least loaded lanes, a cycle of normal round robin scheduling is performed after four rounds of proiritised weighted round robin schedule. The proposed algorithm is simulated and compared with the standard round robin algorithm. The developed algorithm decreases the average waiting time for a commuter while maintaining the average throughput up to average loads. The development traffic monitoring system is successfully demonstrated for a four lane junction.

Design and Implementation of LCG-Trivium Key Stream Generator into FPGA Tchahou Tchendjeu A. E; Tchitnga Robert; Fotsin Hilaire B
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018
Publisher : Institute of Advanced Engineering and Science

This paper presents the Design and implementation into Field ProgrammableGate Array (FPGA) of a combine stream cipher and a simple linear congruential generator circuit to produce key stream. The LCG circuit is used to produce initialization vector (IV) each 264 clock cycle to the cipher trivium in other to strengthen the complexity of the cipher to known attacks on trivium. The LCGTrivium is designed to generate 2144 bits of keystream from an 80-bits secret and a variable 80-bits initial value. To implement the LCG-Trivium on FPGA, we use VHDL to build a simple LCG and Trivium and a state machine to synchronize the functioning of the LCG and Trivium. The number of gates, memory and speed requirement on FPGA is giving after analysis. The design is simulated, synthesized and implemented in Quartus II 10.1, ModelSim-Altera 6.5 and Cyclone IV E EP4CE115F29C7N.

A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique M. Anitha; J.Princy Joice; Rexlin Sheeba.I
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015
Publisher : Institute of Advanced Engineering and Science

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.

FPGA Implementation of Automatic Irrigation and Pesticide Control System D. Hanitha; B. Anusha; M. Durga Prakash
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

In many parts of the world rainfalls are inadequate to meet agricultural needs of farmers. It thus becomes imperative to use an irrigation system that meets the moisture needs of plants in order to increase food crop production. The system described here monitors the moisture and pesticide control needs of crops. Irrigation control is monitored through suitable moisture sensors and automatically pumps water when the need arises through FPGA control logic thus requiring minimal human interventions. We can also use this system for liquid pesticide supply through the selection. Thus, we achieve the efficient supply of water and pesticide as needed by plants and conserve quantity, energy and time. In this paper, the proposed system is designed using Verilog and implemented on FPGA. The system operation is also explained in DSCH (Digital Schematic) software. The system is very simple to operate and ideally suits the irrigation and pesticide need for green houses as well as farms.

Design and implementation of CNTFET based ternary 1x1 memories S.Tamil Selvan; M. Sundararajan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 3: November 2019
Publisher : Institute of Advanced Engineering and Science

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

Arduino controller based borewell child rescue system Melvin Paul Miki.V; S. Prakash; Amarnath. M.K.V; K.Naveen Kumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020
Publisher : Institute of Advanced Engineering and Science

In this paper we have proposed a system for rescuing victims of bore well accidents. The proposed system is light in weight compared to existing methods, portable easy to handle and requires lesser manpower. The system design comprises of a four leg metal stand which supports the whole mechanical assemble the stand is of low weight therefore it is easy to transport it does not requires any heavy duty cranes. This stand has a round housing which holds the DC gear motor which controls the up and down motion of a robotic arm as the arm is connected to the motors shaft with pulley through a rope or heavy duty steel cable. The robotic arm has four mechanically operated fingers which can be opened or closed using a dc motor placed on the arm itself this motor controls the arm by tightening the cables which runs over the four finger joints just like a human arm. The two motors are controlled by an Arduino based remote control module containing buttons and toggle switch with the help of this module easy control of the system is achieved. In addition to this an ultrasonic sensor and a digital camera was also incorporated to predict the victim’s location. In order to determine the feasibility of the system a prototype was designed and fabricated. The prototype consists of all mechanical and electronics setup as discussed above but in a miniature version. The prototype has a control module which consist of LCD display, motor driver IC, Arduino microcontroller, control switches, buttons and power supply unit. This is the main electronics unit which controls and coordinates the whole systems operation. The project is intended to reduce the risk involved during the child rescues operation by analysing the simulation.

An Encyclopedia Coverage of Compiler’s, Programmer’s & Simulator’s for 8051, PIC, AVR, ARM, Arduino Embedded Technologies Anand Nayyar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 1: March 2016
Publisher : Institute of Advanced Engineering and Science

In today’s world, everything from small needle to airplane engineering is surrounded by embedded systems. Embedded System technology not only lays foundation for development but is also acting as Backbone for mankind in almost in every area of science, engineering, research and daily living. The world of embedded systems is mainly surrounded by: Microcontrollers and Microprocessor’s. To work in the area of Embedded Systems design and development is both interesting and challenging- Interesting in the sense, as everything is getting intelligent, advanced and feature rich day by day and the embedded system’s field is progressing by leaps and bounds. But challenging in the way, that resources are very limited in terms of design and implementation. The most important crucial challenges nowadays in front of embedded system engineers are- Which programmer to Use? Which compiler to use for source code development? Which simulator to use to simulate the overall behavior of system? As every compiler, programmer and simulator has distinct features, so selecting the best one as per one’s requirement has always remained a challenge. The main aim of this research paper is to overcome that difficulty by providing the researchers and embedded system engineers an encyclopedic platform of compilers, programmers and simulators for all sorts of embedded system technologies like 8051, PIC, ARM, AVR and Arduino so that choosing of the best platform in terms of compiler, programmer and simulator can become easy and time saving for everyone working in this area.

Page 15 of 46 | Total Record : 456

13 14 15 16 17

Filter by Year

2012 2025

Filter By Issues

All Issue Vol 14, No 3: November 2025 Vol 14, No 2: July 2025 Vol 14, No 1: March 2025 Vol 13, No 3: November 2024 Vol 13, No 2: July 2024 Vol 13, No 1: March 2024 Vol 12, No 3: November 2023 Vol 12, No 2: July 2023 Vol 12, No 1: March 2023 Vol 11, No 2: July 2022 Vol 11, No 1: March 2022 Vol 10, No 3: November 2021 Vol 10, No 2: July 2021 Vol 10, No 1: March 2021 Vol 9, No 3: November 2020 Vol 9, No 2: July 2020 Vol 9, No 1: March 2020 Vol 8, No 3: November 2019 Vol 8, No 2: July 2019 Vol 8, No 1: March 2019 Vol 7, No 3: November 2018 Vol 7, No 2: July 2018 Vol 7, No 1: March 2018 Vol 6, No 3: November 2017 Vol 6, No 2: July 2017 Vol 6, No 1: March 2017 Vol 5, No 3: November 2016 Vol 5, No 2: July 2016 Vol 5, No 1: March 2016 Vol 4, No 3: November 2015 Vol 4, No 2: July 2015 Vol 4, No 1: March 2015 Vol 3, No 3: November 2014 Vol 3, No 2: July 2014 Vol 3, No 1: March 2014 Vol 2, No 3: November 2013 Vol 2, No 2: July 2013 Vol 2, No 1: March 2013 Vol 1, No 3: November 2012 Vol 1, No 2: July 2012 Vol 1, No 1: March 2012 More Issue

Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name
-

Contact Email
-

Phone
-

Journal Mail Official
-

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name -

Contact Email -

Phone -

Journal Mail Official -

Editorial Address -

Location Kota yogyakarta, Daerah istimewa yogyakarta INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Contact Name
-

Contact Email
-

Phone
-

Journal Mail Official
-

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA