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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 456 Documents

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A Novel FPGA based Leading One Anticipation Algorithm for Floating Point Arithmetic Units Ashwini Suresh Deshmukh
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 1: March 2012
Publisher : Institute of Advanced Engineering and Science

In multimedia Systems-on-Chips, the design of specialized IEEE-754-compliant floating point arithmetic units (FPU) is critical with respect to both operating speed and silicon area demand. Leading one anticipation is a well-known issue in the implementation of high speed FPUs. We investigated a novel leading one anticipation algorithm allowing us to significantly reduce the anticipation failure rate with respect to the state-of the art. We embedded our technique into a complete FPU and compared its performance against existing solutions, definitely showing both area savings and total latency reduction.

An Ultra Low Power CMOS Sigma Delta ADC Modulator for System-on-chip (SoC) Temperature Sensor for Aerospace Applications Deepak Prasad; Vijay Nath
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

In the current paper, an accurate with low power consumed sigma delta (ΣΔ) analog to digital converter has been designed for the aerospace applications. The sigma delta ADC has been designed in such a way that it works fine with consumption of low power and high accuracy in the system on chip (SoC) temperature sensor where the analog output from the temperature sensor unit will be the fed to the analog to digital converter. To check the robustness, different parameters with variation has been analyzed. The high gain operational amplifier plays a vital role in the circuits design. Hence, a 30 MHz operational amplifier has also been proposed whose unity gain bandwidth (UGB) has been observed of about 30 MHz, 51.1dB dc gain and slew rate (SR) of about 27.9 V/ μsec. For the proper operation of the circuit, a power supply of +1.3V to -1.3V is used. The proposed sigma delta ADC modulator is showing better results over previously designed modulator in terms of power consumption, error and performance. The design and simulation have been tested with the help of cadence analog design environment with UMC 90nm CMOS process technology.

Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC Arash Farhadi Beldachi; Mohammad Hosseinabady; Jose Luis Nunez-Yanez
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013
Publisher : Institute of Advanced Engineering and Science

New Field Programmable Gate Arrays (FPGAs) are capable of implementing complete multi-core System-on-Chip (SoC) with the possibility of modifying the hardware configuration at run-time with partial dynamic reconfiguration. The usage of a soft reconfigurable Network-on-Chip (NoC) to connect these cores is investigated in this paper. We have used a standard switch developed with the objective of supporting dynamically reconfigurable FPGAs as the starting point to create a novel configurable router. The configurable router uses distributed routing suitable for regular topologies and can vary the number of local ports and communication ports to build multi dimensional networks (i.e., 2D and 3D) with different topologies. The evaluation results show that the selection of the ideal router is different depending on traffic patterns and design objectives. Overall, the mesh network with a four local ports router offers a higher level of performance with lower complexity compared to the traditional mesh with one local port router.

Application of Inverse Perspective Mapping for Advanced Driver Assistance Systems in Automotive Embedded Systems Vighnesh N.T; Rachana Anil; Rohith Kumar D; Sanjana Sharvana; Rajeshwari Hegde; B S Nagabhushana
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 3: November 2017
Publisher : Institute of Advanced Engineering and Science

In the recent times vehicle manufactures and automotive suppliers are progressing towards building vision based subsystems for provisioning driver assistance while targeting the automotive safety critical needs. While the acquired images constitute the fundamental input for any vision based system, transforms on images become essential to derive and gain insight into certain specific features. These derived features are used and reused at multiple places for varied automotive applications. This situation warrants a scalable and flexible image processing platform for a class of automotive applications. An attempt is made in this Research work to propose architecture that, specially, includes a layer of image transformations and to implement a prototype image processing platform. Inverse Perspective Mapping (IPM), a widely used class of transforms is emphasized in the present architecture alongside other nominal transforms. Lane departure warning system is implemented on this platform for the purpose of illustration and to analyze the effectiveness of the proposed architecture

FPGA Based Firewall using Embedded Processor for Vulnarability Packet Detection Mohamed Yousuf Hasan; Poornima V.P; Sujendran S; Karthikraja D
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014
Publisher : Institute of Advanced Engineering and Science

This paper describes the design of high performance packet filtering firewall using embedded system. An FPGA (field programmable gate array) platform has been used for implementation and analysing the network firewall. It is capable of accepting real time changes. This network security application has an ability to perform powerful protection against unwanted data packets such as virus attack, spam in e-mails, hackers, worms, spyware unauthorized contents. However the firewalls don’t address the difficulty of unwanted data packets intrusion. The ultimate aim of this work is to create a systematic way of approach for unwanted packets discard in a network system. We use a specially trained algorithms such as Wu-manber algorithms (high performance, multi-pattern matching), bloom filter algorithm (space efficient data structure for testing an element in the set.Our design is mainly based on machine learning and artificial intelligence. This gives a high efficiency, improved performance and high ability of packet detection with less contribution of time in an effective way.

Verilog based efficient convolution encoder and viterbi decoder Md. Abdul Rawoof; Umasankar Ch.; D. Naresh Kumar; D. Khalandar Basha; N. Madhur
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

In the today’s digital communication Systems, transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.

Implementation of PI Controller for 3ф BLDCM Drive Using FPGA S.M. Ramesh Balaji; C. Muniraj
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 1: March 2015
Publisher : Institute of Advanced Engineering and Science

Despite the need of a complex motor controller, the simple construction of BLDC motors offers several inherent advantages not provided with brushed DC motors in terms of low inertia, high torque and a very wide speed range. The BLDC motors include, Longer service life due to a lack of electrical and friction losses and also free maintenance due to a lack of brushes and mechanical commutators. The EMI and noise are reduced because of the elimination of ionizing spikes from brushes. The control system of BLDCM is highly complex drive due to nonlinear nature. In such a system for implementing control algorithm needs high speed processor. In this work the controller Xilinx Spartan-6 FPGA is a demonstration platform intended to become familiar with the new features and availability of the Spartan-6 FPGA. The various experimental tests are carried out in 3Ф BLDCM .The experimental results are reported in order to verify the steady state, transient and robustness performance of the controller.

Design and implement of high gain and low noise neural amplifier using compensation techniques N. Manikandan; S. Muruganand; K. Karuppasamy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

Electroencephalography is refer to record the electrical signal with respect to brain activity and its reliable EEG information, using this to diagnosis disorder and tumors. However the signal is very difficult to capture and processing due to so many parameter. Mainly this signal is very low range that from 0.1 to 100μv in and its bandwidth range from 1Hz to 100 Hz. So the signal has amplified by using linear and accurate digital program amplifier(PGA).This amplifier has been designed by using First stage amplifier with gain of 120dB with low output noise. The PGA is consists of OPAMPs the PGA change from 10 dB to 120dB.Inorde to optimized the linear and gain accuracy a new structure resister array is proposed high gain PGA. Hence the simulated result has shown it is promising to exhibit an amplifier with high performance biomedical application.

Design and Implementation of Four Bit Binary Shifter Circuit Using Reversible Logic Approach Vandana Shukla; O. P. Singh; G. R. Mishra; R. K. Tiwari
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015
Publisher : Institute of Advanced Engineering and Science

Shifter circuits are the key component of arithmetic logic unit as well as storage unit of any digital computing device. Designing these shifter circuits using reversible logic approach leads to create low power loss digital systems. Reversible circuit design approach is nowadays widely applicable in various disciplines such as Nanotechnology, Low power CMOS design, Optical computing etc. This paper presents two design approaches for four bit binary combinational shifter circuit with the help of different types of reversible logic gates. The proposed optimized design is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.

An FPGA Implementation of On Chip UART Testing with BIST Techniques P Bala Gopal; K Hari Kishore
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.

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