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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 479 Documents

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Controller for Network Interface Card on FPGA Suchita Kamble; N. N. Mhala
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012
Publisher : Institute of Advanced Engineering and Science

The continuing advances in the performance of network servers make it essential for network interface cards (NICs) to provide more sophisticated services and data processing. Modern network interfaces provide fixed functionality and are optimized for sending and receiving large packets. Network interface cards allow the operating system to send and receive packets through the main memory to the network. The operating system stores and retrieves data from the main memory and communicates with the NIC over the local interconnect, usually a peripheral component interconnect bus (PCI). Most NICs have a PCI hardware interface to the host server, use a device driver to communicate with the operating system and use local receive and transmit storage buffers. NICs typically have a direct memory access (DMA) engine to transfer data between host memory and the network interface memory. In addition, NICs include a medium access control (MAC) unit to implement the link level protocol for the underlying network such as Ethernet, and use a signal processing hardware to implement the physical (PHY) layer defined in the network. To execute and synchronize the above operations NICs also contents controller whose architecture is customized for network data transfer. In this paper we present the architecture of application specific controller that can be used in NICs.

Universal Automobile Headlight Control Module for High Beam Adaptation during Night Vision Travel an Embedded Design Approach M. Subramania Siva; G. Jeyakumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

Road accidents during night travel increases day by day and vision impairment due to high beam contributes to the majority of the total fatalities. Headlights of vehicles pose a great danger during night driving. [1] The drivers of most vehicles use high/bright beam while driving at night. This causes a discomfort to the person travelling from the opposite direction. The driver experiences a sudden glare caused due to the high intense headlight beam from the other vehicle coming towards him from the opposite direction. We are expected to dim the headlight to avoid this glare. This glare causes a temporary blindness to a person resulting in road accidents during the night. To avoid such incidents, an embedded prototype of Automatic Headlight adaptor module is proposed. This embedded module automatically switches the high beam to low beam and returns backs to high beam, thus reducing the sudden glare effect. It also eliminates the requirement of manual switching by the driver to switch back to low beam Universal Headlight adaptor module is a unique solution to achieve the above objective, the headlight intensity of the incoming vehicles causing the glare is automatically attenuated to low beam wirelessly by the nearby vehicles affected by high beam. The interconnected modules at every vehicle independently takes the decision on the head light control of the source vehicle causing the glare by evaluating various parameters like vehicle speed, current GPS location, direction of vehicle etc.

Low Power VLSI Design and Implementation of Area-Optimized 256-bit AEStandard for Real Time Images on Vertex 5 Shruthi AV; Electa Alice; Mohammed Bilal
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013
Publisher : Institute of Advanced Engineering and Science

A new Vertex6-chipscope based implementation scheme of the AES-256 (Advanced Encryption Standard, with 256-bit key) encryption and decryption algorithm is proposed in this paper. For maintaining the speed of encryption and decryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 256-bit plaintext and the 256- bit initial key, as well as the 256-bit output of cipher-text, are all divided into four 32-bit consecutive units respectively controlled by the clock. In this novel work, substantial improvement in performance in terms of area, power and dynamic speed has been obtained.

Metal Oxides Semiconductor Sensors for Odor Classification Nyayu Latifah Husni; Ade Silvia; Siti Nurmaini; Irsyadi Yani
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 3: November 2017
Publisher : Institute of Advanced Engineering and Science

The performance of gas sensor will differ and vary due to the surrounding environment changing, the way of implementation, and the position of the sensors to the source. To reach a good result on gas sensors implementation, a performance test on sensors is needed. The results of the tests are useful for characterizing the properties of the particular material or device. This paper discusses the performances of metal oxides semiconductor (MOS) sensors. The sensors are tested to determine the sensors' time response, sensors' peak duration, sensors' sensitivity, and sensors' stability of the sensor when applied to the various sources at different range. Three sources were used in experimental test, namely: ethanol, methanol, and acetone. The gas sensors characteristics are analyzed in open sampling method in order to see the sensors' sensitivity to the uncertainty disturbances, such as wind. The result shows that metal oxides semiconductor sensor was responsive to the 3 sources not only in static but also dynamic conditions. The expected outcome of this study is to predict the MOS sensors' performance when they are applied in robotic implementation. This performance was considered as the training datasets of the sensor for odor classification in this research. From the experiments, It was got, in dynamic experiment, the senrors has average of precision of 93.8-97%, the accuracy 93.3-96.7%, and the recall 93.3-96.7%. This values indicates that the sensors were selective to the odor they sensed.

FPGA based Multichannel Bit Error Rate Tester for Spacecraft Data Acquisition System Manoj Kumar A; R V Nadagouda; R Jegan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014
Publisher : Institute of Advanced Engineering and Science

Bit Error Rate (BER) is a principle measure of data transmission link performance. BER tester (BERT) consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of one, two or three channels per carrier based on the modulation scheme. The traditional equipments can do BER analysis for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix II (EP2S130F1508C5N) FPGA. Ethernet is configured using WIZnet 5300 (Ethernet Controller) and it is used for communication between FPGA and PC with an application. Application is used to transmit the Pattern Generator’s configurations from PC to FPGA and to receive Analyzer’s status. Packet processing is done for this communication using User Datagram protocol (UDP). On the whole, traditional equipments are replaced by the designed and implemented bit error rate tester.

Design and software characterization of finFET based full adders Raju Hajare; C. Lakshminarayana
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Adder is the most important arithmetic block that are used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.

An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems Ahmed Al-Wattar; Shawki Areibi; Gary Grewal
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 2: July 2015
Publisher : Institute of Advanced Engineering and Science

Several embedded application domains for reconfigurable systems tend to combine frequent changes with high performance demands of their workloads such as image processing, wearable computing andnetwork processors. Time multiplexing of reconfigurable hardware resources raises a number of new issues, ranging from run-time systems to complex programming models that usually form a Reconfigurablehardware Operating System (ROS). The Operating System performs online task scheduling and handles resource management.There are many challenges in adaptive computing and dynamic reconfigurable systems. One of the major understudied challengesis estimating the required resources in terms of soft cores, Programmable Reconfigurable Regions (PRRs), the appropriate communication infrastructure, and to predict a near optimal layout and floor-plan of the reconfigurable logic fabric. Some of these issues are specific to the application being designed, while others are more general and relate to the underlying run-time environment.Static resource allocation for Run-Time Reconfiguration (RTR) often leads to inferior and unacceptable results. In this paper, we present a novel adaptive and dynamic methodology, based on a Machine Learning approach, for predicting andestimating the necessary resources for an application based on past historical information.An important feature of the proposed methodology is that the system is able to learn and generalize and, therefore, is expected to improve its accuracy over time. The goal of the entire process is to extract useful hidden knowledge from the data. This knowledge is the prediction and estimation of the necessary resources for an unknown or not previously seen application.

Analysis of Different Ways of Crosstalk Measurement in GSM Network Musefiu Aderinola; Bokolo Abovie; Festus Okosi; Igoniderigha Daniel; G.F. Odubo
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 2: July 2016
Publisher : Institute of Advanced Engineering and Science

Crosstalk is one of the problems that affect the performance operation of global system mobile (GSM) network. Among the effect of crosstalk are call mute, call drop, wire propagation delay, dynamic power dissipation etc. Crosstalk is an undesirable signal arising due to the coupling capacitances between adjacent interconnecting wires and measured in decibel. In this paper some literature were reviewed and different ways of measuring crosstalk such as Near end croosstalk (NEXT), far end crosstalk (FEXT), Power sum crosstalk (PSNEXT) and alien crosstalk (AXT) were analyzed.

Live tracking of saline for betterment of patient Sayli Anand Zende; Tanvi Kulkarni; Shubhada Yadav; Ajay Biradar; Avinash Devare
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp178-182

In hospitals, Saline is fed to patients to treat dehydration and use of saline improves their health. In current health care measures, whenever a saline is fed to any patient, the patient must be continuously monitored by nurse, doctor or caretaker. So basically, in all the hospitals nurse or caretaker is responsible for monitoring of saline. Due to the avoidance of nurses towards the saline level monitoring or lack of knowledge it can harm to the patients health. Therefore, to stop the patient from obtaining injured and shield their lives throughout saline feeding amount, the saline level observance system are developed. The planned system is made Internet web of Things (IoT) platform. The planned system includes of devices which can act as tier sensor for observance the crucial level of the saline within the saline bottle. Whenever the amount of the saline reaches to the predefined crucial level, then the nurses, caretaker, doctors are alerted through the alarm associate in Nursing an alert message are sent through the utilization of web to the involved nurses and doctors that there's a requirement for replacement of the saline bottle. This planned system may be utilized efficiently in homes as well as hospitals.

FAST LOCAL FLOW-BASED METHOD USING PARALLEL MULTI-CORE CPUS ARCHITECTURE Moneim, Wafaa Abdel; Salem, Rashed; Hassan, Mohamed
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp%p

Large graphs are available in everywhere such as social networks, chemistry, web link analysis, biology, image processing, and computer networks. Traditional methods of clustering are not suitable to solve this problem due to the computation is very costly. This problem is solved by local graph clustering using a given vertex set as input without working on the complete graph to detect a good cluster. SimpleLocal is introduced and analyzed for locally-biased graph-based learning. This algorithm detects a best conductance cuts close to seed vertices set. In this paper, a new Parallel SimpleLocal (PSL) system is proposed using multi-core CPUs. OMP parallel library is utilized to parallelize the first and second stages of 3StageFlow algorithm where the SimpleLocal algorithm is used it for enhancing the runtime. The experiments are performed on two applications which are image segmentation and community detection. From the experiments, the proposed method improves the runtimes with 72.75% using 4-cores and 81.01% when using 8-cores over the sequential single core

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