International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
456 Documents
<![CDATA[Implementation of LOCO-I Lossless Image Compression Algorithm for Deep Space Applications ]]>
<![CDATA[P. Praveena]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
Full PDF (84.304 KB)
|
DOI: 10.11591/ijres.v3.i1.pp25-30
<![CDATA[Present emerging trend in space science applications is to explore and utilize the deep space. Image coding in deep space communications play vital role in deep space missions. Lossless image compression has been recommended for space science exploration missions to retain the quality of image. On-board memory and bandwidth requirement is reduced by image compression. Programmable logic like field programmable gate array (FPGA) offers an attractive solution for performance and flexibility required by real time image compression algorithms. The powerful feature of FPGA is parallel processing which allows the data to process quicker than microprocessor implementation. This paper elaborates on implementing low complexity lossless image compression algorithm coder on FPGA with minimum utilization of onboard resources for deep space applications.]]>
<![CDATA[Real time FPGA Implementation of PWM Chopper Fed Capacitor Run Induction Motor ]]>
<![CDATA[N. Murali]]>;
<![CDATA[V. Balaji]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
Full PDF (545.057 KB)
|
DOI: 10.11591/ijres.v7.i3.pp138-148
<![CDATA[This paper presents the performance enhancement of capacitor run induction motor by pulse width modulated AC chopper.The phase angle control faces severe shortfall in the performance improvement for larger triggering angles. In this paper the comparison of phase angle control and sinusoidal pulse width modulation technique is encountered for effective speed control of single phase capacitor run induction motor. The necessary parameters are taken into considerations are higher efficiency, lesser total harmonic distortion and high input power factor. The results are compared by using the simulations using matlab Simulink environment. The validation of result in hardware is implemented using Field programmable gate array for sinusoidal pulse width modulation technique.]]>
<![CDATA[Design and Development of Low Cost Navigation and Security System for Indian Fisherman Using Adrino Nano Platform ]]>
<![CDATA[Sanket Dessai]]>;
<![CDATA[Mahir M.M.]]>;
<![CDATA[Mayur R.]]>;
<![CDATA[Nilkantha Singha]]>;
<![CDATA[Vinutha Avaradhi]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 1: March 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
Full PDF (1098.959 KB)
|
DOI: 10.11591/ijres.v4.i1.pp28-41
<![CDATA[The fishing industry plays a major role in development of Indian economy. The recent attacks on fishermen taking place in Indo-Srilanka and Indo-Pakistan maritime boundaries have been major concerns. These attacks are primarily caused by the lack of navigation and security features during the voyage. Hence the current situation demands the implementation of precise facilities for reducing man and material loss. This project involves the design and implementation of a Low cost Navigation and Security System for Indian fishermen on Arduino Nano platform. The system developed solves the above said issues by continously tracking the location of fishing vessel and providing minimal security features. The system ensures that navigation is in safe zone within the nation’s maritime boundary and also prevents crossover. This is acheived using GPS receiver which directly links to GPS satellites for current location of the vessel. The required data fields like the latitude and longitude data along with the time stamps are extracted from the GPS samples and used for comparision for determining the exact location of the vessel. This procedure will help in detection of corner cases when the vessel is nearing or about to crossover the maritime boundary, which cannot be marked physically. It is useful for triggering conditions like enabling or disabling fuel injection system, the warning beeps and display notifications to the fishermen. Manual override facility for restarting the engine in case of crossover for limited duration is provided. The security features like authentication for the genuine operator to get access to the engine panel, the support for distress message and the storage of the exact time stamps and GPS locations after encryption in case of initiation of transmitting distress message is provided as a blackbox feature. The passcode based mechanism allows for maximum of three attempts to unlock access to control panel. The GSM modem allows for transmission of distress message to the registered base station/coast guard. The encrypted GPS samples and time stamps are stored in on-chip EEPROM memory for future reference. ]]>
<![CDATA[Notice of Retraction: Implement embedded controller using FPGA chip ]]>
<![CDATA[Haresh Pandya]]>;
<![CDATA[Mahesh Rangapariya]]>;
<![CDATA[Jitendra Rajput]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
Full PDF (886.887 KB)
|
DOI: 10.11591/ijres.v8.i2.pp130-144
<![CDATA[This article has been retracted by the publisher.Notes: Notice of Retraction: After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IAES's Publication Principles. We hereby retract the content of this paper. Reasonable effort should be made to remove references to this paper. The presenting author of this paper has the option to appeal this decision by contacting info@iaesjournal.com.------------------------------------The designer of an FPGA embedded processor system has complete flexibility to select any combination of peripherals and controllers. In fact, the designer can invent new, unique peripherals that can be connected directly to the processor bus. If a designer has a non-standard requirement for a peripheral set, this can be met easily with an FPGA embedded processor system. For example, a designer would not easily find an off-the-shelf processor with ten UARTs. However, in an FPGA, this configuration is very easily accomplished.]]>
<![CDATA[Design and Implementation of Recursive Least Square Adaptive Filter Using Block DCD approach ]]>
<![CDATA[Sachin S. Khanande]]>;
<![CDATA[S.J. Honade]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
Full PDF (133.074 KB)
|
DOI: 10.11591/ijres.v4.i3.pp209-212
<![CDATA[Due to the explosive growth of multimedia application and tremendous demands in Very Large Scale Integrated (VLSI), there is a need of high speed and low power digital filters for digital signal processing applications. In Digital Signal Processing (DSP) systems, Finite Impulse Response (FIR) filters are one of the most common components which is used, by convolving the input data samples with the desired unit sample response of the filter. The proposed work deals with the design and implementation of RLS adaptive filter using block DCD approach. The evaluation of speed, area and power for proposed work will be done. Also, the comparison of the proposed design with the existing will be carried out for various input combinations.]]>
<![CDATA[A Gracefully Degrading and Energy-Efficient FPGA Programming using LabVIEW ]]>
<![CDATA[B. Naresh Kumar Reddy]]>;
<![CDATA[N. Suresh]]>;
<![CDATA[J.V.N. Ramesh]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
Full PDF (879.099 KB)
|
DOI: 10.11591/ijres.v5.i3.pp160-169
<![CDATA[Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.]]>
<![CDATA[A scalable FPGA based accelerator for Tiny-YOLO-v2 using OpenCL ]]>
<![CDATA[Yap June Wai]]>;
<![CDATA[Zulkanain Mohd Yussof]]>;
<![CDATA[Sani Irwan Md Salim]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 3: November 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
Full PDF (779.62 KB)
|
DOI: 10.11591/ijres.v8.i3.pp206-214
<![CDATA[Deep Convolution Neural Network (CNN) algorithm have recently gained popularity in many applications such as image classification, video analytic, object recognition and segmentation. Being compute-intensive and memory expensive, CNN computations are common accelerated by GPUs with high power dissipations. Recent studies show implementation of CNN on FPGA and it gain higher advantage in term of energy-efficient and flexibility over Software-configurable-GPUs. The proposed framework is verified by implement Tiny-YOLO-v2 on De1SoC. The design development in this project is HLS approach to ease effort from writing complex RTL codes and provide fast verification through emulation and profiling tools provided in the OpenCL SDK. To best of our knowledge, this is the first implementation of Tiny-YOLO-v2 CNN based object detection algorithm on a small scale De1SoC board using Intel FPGA SDK for OpenCL approach.]]>
<![CDATA[Space-time trellis codes: Field programmable gate array approach ]]>
<![CDATA[Mallikarjuna Gowda C. P.]]>;
<![CDATA[Raju Hajare]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
DOI: 10.11591/ijres.v9.i3.pp213-223
<![CDATA[This paper presents an implementation of Space-time Trellis Codes for 4-state on FPGA. To reach the very high data rates provided in STTC, a lot of expensive high-speed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in which the STTC encoder and decoder utilizes maximum 10% and 22% as that of available device capacity respectively. The design has been simulated and synthesized successfully in Xilinx integrated software environment.]]>
<![CDATA[Simulation and Real Time Implementation of Various PWM Strategies for 3 Φ Multilevel Inverter Using FPGA ]]>
<![CDATA[C. R. Balamurugan]]>;
<![CDATA[S. P. Natarajan]]>;
<![CDATA[T. S. Anandhi]]>;
<![CDATA[B. Shanthi]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
Full PDF (1165.178 KB)
|
DOI: 10.11591/ijres.v6.i1.pp1-19
<![CDATA[For high power applications Multilevel Inverter (MLI) is extensively used. The major advantages of MLI are good power quality, low switching losses and maintenance of the desired voltage. In this work, the three phase cascaded multi level inverter is analyzed under various modulation techniques that include Sub-Harmonic Pulse Width Modulation (SHPWM) i.e. Phase Disposition (PD) strategy, Phase Opposition Disposition (POD) strategy, Alternate Phase Opposition Disposition (APOD) strategy, hybrid strategy (PD and PS) and Phase Shift (PS) strategy. The study will help to choose those techniques with reduced harmonics for the chosen three phase cascaded MLI with R-L load. The Total Harmonic Distortion (THD), VRMS (fundamental), crest factor and form factor are evaluated for various modulation indices at two different switching frequencies (3.15KHz and 6 KHz). Simulation is performed using MATLAB-SIMULINK. It is observed that HYBRID PWM and PSPWM methods provide output with relatively low distortion for low and high switching frequencies. PODPWM and PSPWM are found to perform better since they provide relatively higher fundamental RMS output voltage for 6 KHz and 3.15 KHz switching frequencies. The experimental result shows PSPWM provide output with low distortion and HYBRID PWM provide output with higher fundamental RMS voltage for fc=3.15KHz. The experimental results were obtained only for fc=3.15KHz.]]>
<![CDATA[VHDL Implementation of H.264 Video Coding Standard ]]>
<![CDATA[Haresh A. Suthar]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
Show Abstract
|
Download Original
|
Original Source
|
Check in Google Scholar
|
Full PDF (615.053 KB)
|
DOI: 10.11591/ijres.v1.i3.pp95-102
<![CDATA[This Paper contains VHDL implementation of H.264 video coding standard, which is new video coding standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The main goal of the H.264/AVC standardization effort is to enhance compression performance and provision of a “network-friendly” video representation addressing “conversational” (video telephony) and “no conversational” (storage, broadcast, or streaming) applications.H.264 video coder standard is having fundamental blocks like transform and quantization, Intra prediction, Inter prediction and Context Adaptive Variable Length Coding (CAVLC). Each block is designed and integrated to one top module in VHDL.]]>
