International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
479 Documents
<![CDATA[Efficient robust speech recognition with empirical mode decomposition using an FPGA chip with dual core ]]>
<![CDATA[Shing-Tai Pan]]>;
<![CDATA[Ching-Fa Chen]]>;
<![CDATA[Wen-Sin Tseng]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp109-115
<![CDATA[The purpose of this paper is to accelate the computing speed of Empirical Mode Decomposition (EMD) based on multi-core embedded systems for robust speech recognition. A reconfigurable chip, Field Programmable Gate Array (FPGA), is used for the implementation of the designed system. This paper applies EMD to discompose some noised speech signals into several Intrinsic Mode Functions (IMFs). These IMFs will be combined to recover the original speech by multiplying their corresponding weights which were trained by Genetic Algorithms (GA). After applying Empirical Mode Decomposition (EMD), we obtain a cleaner speech for recognition. Due to the complexity of the computation of the EMD, a dual-core architecture of embedded system on FPGA is proposed to accelerate the computing speed of EMD for robust speech recognition. This will enhance the efficiency of embedded speech recognition system.]]>
<![CDATA[Implementation of PWM AC chopper controller for capacitor run induction motor drive via bacterial foraging optimization algorithm ]]>
<![CDATA[Gobi Mohan Sivasubramanian]]>;
<![CDATA[Murali Narayanamurthy]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i3.pp169-177
<![CDATA[This paper focuses on design of closed-loop control for pulse width modulated AC chopper controlled capacitor run induction motor drive engaging enriched optimization algorithm based on foraging of bacteria. Capacitor run induction motor is a non-linear device and its parameter varies under different functional point of the system. A linearized increment model for PWM AC chopper is illustrated for a particular functional point of the drive. The conventional method does not provide acceptable performance under different load conditions. Bacteria foraging optimization technique categorizes accurate control parameters for the superlative dynamic response under unit step load variations. Field Programmable Gate Array is implemented practically for a particular functional point of the drive to exhibit accurate performance. Experimental and simulated results are obtained to authenticate the effectiveness of the optimized controller. ]]>
<![CDATA[FPGA-based Architecture of Direct Torque Control ]]>
<![CDATA[Azaza Maher]]>;
<![CDATA[Echaieb Kamel]]>;
<![CDATA[Mami Abdelkader]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i1.pp20-27
<![CDATA[This paper presents an optimized FPGA architecture of a DTC “direct torque control” drive of an induction motor. The proposed architecture is based on variable fixed point world size and the use ipcores in order to achieve higher sampling frequency which leads to reduce the electromagnetic torque and flux ripples. The hardware implementation was experimentally validated, the results shows the effectiveness of the hardware DTC drive implementation by the minimization of the torque and flux ripple]]>
<![CDATA[Attendance Logging In Webserver Using Multi Node Embedded System Connected Through Wi-Fi ]]>
<![CDATA[Mohammed Bilal]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v1.i3.pp103-107
<![CDATA[In the present age, we are in need of fully automated attendance logging system. The design of Remote Attendance Logging System and its control is a challenging part. RFID reader reads the RFID tag, and the details of the tag is logged in the embedded system. The Web based distributed measurement and control is slowly replacing parallel architectures due to its non-crate architecture which reduces complexities. A new kind of expandable, distributed large attendance logging system based on ARM Cortex M3 boards has been investigated and developed in this paper, whose hardware boards use 32-bit RISC processor with wifi dongle attached to its USB port, and software platform use Keil MDK-ARM for firmware and HTML for man machine interface. This system can display date and time of log in and log out of a person. The data can be displayed on web pages at different geographical locations, and at the same time can be transmitted to a Remote Data Acquisition System by using HTTP protocol. The embedded board can act as a central CPU to communicate between web servers automatically.]]>
<![CDATA[Using FPGA Design and HIL Algorithm Simulation to Control Visual Servoing ]]>
<![CDATA[Lway Faisal Abdulrazak]]>;
<![CDATA[Zaid A. Aljawary]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 2: July 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i2.pp111-119
<![CDATA[This is a novel research paper provides an optimal solution for object tracking using visual servoing control system with programmable gate array technology to realize the visual controller. The controller takes in account the robot dynamics to generate the joint torques directly for performing the tasks related to object tracking using visual servoing. Also, the notion of dynamic perceptibility provides the capability of the designed system to track desired objects employing direct visual servoing technique. This idea is assimilated in the suggested controller and realized in the programmable gate array. Additionally, this paper grants an ideal control framework for direct visual servoing robots that incorporates dynamic perceptibility features. With the aim of evaluating the proposed FPGA based architecture, the control algorithm is applied to Hardware-in-the-loop simulation (HIL) set up of three degrees of freedom rigid robotic manipulator with three links. Furthermore, different investigations are performed to demonstrate the behavior of the proposed system when a trajectory adjacent to a singularity is attained.]]>
<![CDATA[FPGA Based Embedded System Development for Rolling Bearings Fault Detection of Induction Motor ]]>
<![CDATA[Shashidhara SM]]>;
<![CDATA[Sangameswara P Raju]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 3: November 2013 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v2.i3.pp127-134
<![CDATA[Bearing fault diagnosis is crucial in condition monitoring of any rotating machine. Early fault detection in machines can save millions of dollars in maintenance cost. Different methods are used for fault analysis such as short time Fourier transforms (STFT), Wavelet analysis (WA), Model based analysis, cepstrum analysis etc. Recently, there have been outstanding technological developments related to digital systems, in both hardware and software. These innovations enable the development of new designing methodologies that aim to the ease the future modifications, upgrades and expansions of the system. This paper presents a study of rolling bearing fault diagnosis of induction motor based on reconfigurable logic. A case study using FPGA, its design, as well as its implementation and testing, are presented.]]>
<![CDATA[New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology ]]>
<![CDATA[Houda Ghabri]]>;
<![CDATA[Dalenda Ben Issa]]>;
<![CDATA[Hekmet Samet]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v7.i3.pp195-202
<![CDATA[The heart of the microprocessor and responsible for the execution of logical and arithmetic operations, the arithmetic and logical unit is constantly optimized. The performance is improved to allow the development of more powerful and smaller circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double-gate carbon nanotube field effect transistor (DG-CNTFETs). This transistor has an interesting property, it can switch from p- to n- type behavior and vice-versa dynamically. This opens the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs and reaching a good performance levels. In literature there are several problems related to signal quality. In this paper, we will propose a new solution that allows us to improve the quality of the output signal without affecting the number of transistors used. This improves the overall performance of ALU. We will show the improvement in signal level and quality. First, an overview of carbon nanotube field-effect transistor (CNTFET) and state of the art Reconfigurable ALU based on DG-CNTFET is given. Then an explication of signal integrity issues of the actual Reconfigurable DG-CNTFET cell is done. After we will present and explain the proposed solution. The solution is first applied on the cnt_9T circuit then will show its effect on the ALU. Finally, a performance comparison is made.]]>
<![CDATA[Wireless Sensor Network for Performance Monitoring of Electrical Machine ]]>
<![CDATA[Priyanka Ranaware]]>;
<![CDATA[N.D. Dhoot]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 1: March 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i1.pp1-5
<![CDATA[This paper proposes a novel industrial wireless sensor network for industrial machine condition monitoring. To avoid unexpected equipment failures and obtain higher accuracy in diagnostic and prognostic for the health condition of a motor, efficient and comprehensive data collecting, monitoring, and control play an important role to improve the system more reliable and effective. A novel wireless data collection for health monitoring system of electric machine based on wireless sensor network is proposed and developed in this paper. The unique characteristics of ZigBee networks such as low power, low cost, and high flexibility make them ideal for this application. The proposed system consists of wireless sensor nodes which are organized into a monitoring network by ZigBee protocols. A base station and wireless nodes have been developed to form a prototype system. Various sensors have the capability to monitor physiological as well as environmental conditions. Therefore proposed system provides a flexible solution that makes our living spaces more intelligent.]]>
<![CDATA[Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders ]]>
<![CDATA[Nehru.K K]]>;
<![CDATA[Nagarjuna T]]>;
<![CDATA[Somanaidu U]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v7.i2.pp115-123
<![CDATA[Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes with the lowest transistor count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.]]>
<![CDATA[Design of Low Power Dual Dynamic Node Flip-Flop Using Sleep Transistor with NMOS ]]>
<![CDATA[Ajeesh Kumar]]>;
<![CDATA[N. Saraswathi]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i3.pp178-184
<![CDATA[This paper introduces a Low Power Dual DynamicNode FlipFlop(DDFF) using Sleep Transistor with NMOS. Theproposed design retains the logic level till the end of evaluation and pre-charge mode. The low power DDFF architecturethat combines the advantages of dynamic and static CMOSstructures. The Sleep Transistors approach are used for leakagepower reduction. It reduces leakage current in ideal mode.The performance of the proposed flip flop was compared withthe conventional dual dynamic node flip flop (DDFF) in 90nmCMOS technology with 1.2v supply voltage at room temperatures.Also, conventional DDFF and DDFF using Sleep Transistor withNMOS are compared with other complicated designs and realizesby a 4-bit Johnson up and down counter. The performanceimprovements indicates that the proposed designs are suited formodern high-performance CMOS circuits where leakage powerand power delay product overhead are of major concern]]>
