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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 456 Documents
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FPGA Based Data Hiding Methods using DNA Cryptography Techniques B. Murali Krishna; CH. Surendra; K. Mani Varma; K. Mani Kanta; S.K. Shabbeer; G.L. Madhumati
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (524.958 KB) | DOI: 10.11591/ijres.v5.i3.pp137-142

Abstract

To convey the information safely DNA grouping mechanisms are used. There are many methods used by DNA sequences. The proposed method is of both encryption and information concealing utilizing a few properties of Deoxyribonucleic Acid (DNA) groupings. This technique is highlighted that DNA groupings have many more intriguing properties which are used for concealing the information. There are three strategies in this encryption strategy: the Insertion Technique, the Complimentary Pair Technique and the Substitution Strategy .For every single strategy, a specific reference DNA grouping P is chosen and then the taken sequence is changed over with the mystery message M and is consolidated, so that P0 is acquired. P0 is then sent to the collector and the beneficiary can recognize and separate the message M covered up in P. This technique is proposed to utilize INSERTION Strategy. Subsequently, the proposed plan comprises for the most part of two stages. In the principal stage, the mystery information is encoded utilizing a DNA Sequence. In the second stage the encoded information is steganographically covered up into some reference DNA grouping utilizing an insertion strategy. The effectiveness of this security algorithm is seen with many merits and limitations. A, C, G, and T are the 4 nucleotides which are taken for this project.
Surface potential modeling of dual metal gate-graded channel-dual oxide thickness with two dielectric constant different of surrounding gate MOSFET Hind Jaafar; Abdellah Aouaj; A. Bouziane; Benjamin Iñiguez
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 1: March 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (502.872 KB) | DOI: 10.11591/ijres.v9.i1.pp52-60

Abstract

An Analytical study for the surface potential, threshold voltage and Subthreshold swing (SS) of Dual-metal Gate Graded channel and Dual Oxide Thickness with two dielectric constant different cylindrical gate surrounding-gate (DMG-GC-DOTTDCD) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, threshold voltage shift, and Subthreshold swing. It is shown that the novel MOSFET could significantly reduce threshold voltage shift and Subthreshold swing, can also provides improved electron transport and reduced short channel effects (SCE). Results reveal that the DMG-GC-DOTTDCD devices with different dielectric constant offer superior characteristics as compared to DMG-GC-DOT devices. The derived analytical models agree well with simulation by ATLAS.
Modern design approach of faults (toggling faults, bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks Kurada Veera Bhoga Vasantha Rayudu; Jahagirdar Jahagirdar; P Rao
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (582.953 KB) | DOI: 10.11591/ijres.v9.i2.pp158-168

Abstract

In this Research we are going to develop ROBDD (Reduced Ordered Binary Decision Diagram) designs to detect toggling faults, bridge faults and SAT (Stuck at Fault), Here we are going to develop sequential blocks using ROBDD and applying to the mux to detect stuck at faults and also connecting the combo & Sequential blocks to find the toggling faults by connecting or using automatic test pattern generator. In this research we are going to develop the bridges between the blocks of ROBDD designs and converting them to and or logic to find the bridge faults of the design. Finding bridge and toggle faults are more difficult in logic designs, here we use an advance technique to find the faults of the design by calculating the path delays of the individual blocks of the design. More concentrating on the path delays by using basic stuck at faults methods to refer the faults (toggling and bridge faults) at mux output. In our research the basic design modules are ROBDD circuit of both combinational and sequential blocks are designed and tested using Multiplexer and K-map Simplification Methods. The main purpose of the research to find the faults at all levels of all logic designs which involves in both combinational and sequential blocks of the design.
Substrate integrated circuits for high frequency of opto electronics Mounika Punati; R. Yuvaraj
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp224-228

Abstract

Another age of high-recurrence coordinated circuits is displayed, which is called substrate incorporated circuits (SICS). The current cutting edge of circuit plan and implementation stages dependent on this new idea are assessed and discussed in detail. Various potential outcomes and various favorable circumstances of the SICS are appeared for microwave, millimeter-wave and opto hardware applications. Down to earth models are delineated with hypothetical and trial results for substrate coordinated waveguide (SIW), substrate incorporated chunk waveguide (SISW) and substrate incorporated non-transmitting dielectric (SI") direct circuits. Future innovative work patterns are likewise dis-cussed regarding ease imaginative plan of millimeter-wave and optoelectronic coordinated circuits.
Hamming neural network application with FPGA device Liqaa Saadi Mezher
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i1.pp37-46

Abstract

The Hamming neural network is a kind of counterfeit neural system that substance of two kinds of layers (feed forward layers and repetitive layer). In this study, two pattern entries are utilization in the binary number. In the first layer, two nerves were utilization as the pure line work. In the subsequent layer, three nerves and a positive line work were utilization. The Hamming Neural system calculation was also implemented in three reproduction strategies (logical gate technique, programming program encryption strategy and momentary square chart technique). In this study in programming of VHDL and FPGA machine was utilization.
Approximate arithmetic circuits Navabharath Reddy G; Sruti Setlam; V. Prakasam; D. Kiran Kumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp183-200

Abstract

Low power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia applications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation is less, the output of the DSP blocks allows being numerically approximate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. An Approximate 4-2 compressor was proposed in this project to reduce the number of partial product. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1 took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW) which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier.
Automated smart car parking system using raspberry Pi 4 and iOS application Rahman Atiqur; Yun Li
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp229-234

Abstract

In interconnection and automation of different physical gadgets, vehicles, home machines and different things, the internet of things (IoT) innovation plays a critical role. These objects associate and deal information with the assistance of software, different sensors, and actuators. A human's standard of life and living are improved with this automation of gadgets, which is a forthcoming need. In this paper we talked about a similar requirement for instance, a smart car parking system which empowers a driver to discover a parking area and a free slot in that parking area inside a city. This paper focus on decreasing the time squandered on discovering parking area. This in turn diminishes the fuel utilization and way of life. With the exponential increment in the quantity of vehicles and total population, vehicle accessibility, use out, about starting late, finding a space for parking the vehicle is turning out to be increasingly more troublesome with realizing the amount of conflicts, for example, automobile overloads. This paper is connected to making a trustworthy system that accept authority over the undertaking of recognizing free slots in a parking area and keeping the record of vehicles left in an extremely methodical way. The predicted system decreases human effort at the parking area generally, for example, in case of looking of free slots by the driver and calculating the portion for each vehicle using parking area. The different advances engaged with this system are vehicle unique proof utilizing RFID labels; free slot discovering utilizing Ultrasonic sensors and payment count is done based on time of parking.
Restoration circuits for low power reduce swing of 6T and 8T SRAM cell with improved read and write margins Ram Murti Rawat; Vinod Kumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 2: July 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i2.pp130-136

Abstract

This article clarifies about the variables that influence the static noise margin (SNM) of a static random-access memory. Track down the improved stability of proposed 8T SRAM cell which is superior to conventional 6T SRAM cell utilizing Swing Restored circuit with voltages Q and QB bar are peruse and Compose activity. This SRAM cell strategy on the circuit or engineering level is needed to improve read static noise margin (RSNM), write static noise margin (WSNM) and hold static noise margin (HSNM). This article relative investigation of conventional 6T, standard 8T and proposed 8T SRAM cells with improved stability and static noise margin is finished for 180 nm CMOS innovation. This paper is coordinated as follows: Introduction in area 1, The 6T SRAM cell are portrayed in segment 2. In area 3, proposed 8T SRAM cell is portrayed. In area 4, standard 8T SRAM cell. Segment 5 incorporates the simulation and results which give examination of different boundaries of 6T and 8T SRAM cells and segment 6 conclusions.
Ultra high speed full adder for biomedical applications Basavoju Harish; M. S. S. Rukmini
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i1.pp25-31

Abstract

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.
Characterization and hierarchical static timing analysis of mixed-signal design Sowmya K. B.; Thanushree M.
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 10, No 1: March 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v10.i1.pp18-24

Abstract

As the technology grows, the tendency to increase the data rate also increases. Clocks with higher frequencies have to be generated to meet the increased data rate. Any mismatch between the clock rate and data rate will lead to the capture of the wrong data. Hence performing timing analysis for any design to validate the capture of correct data plays a major role in any System on chip. This paper explains the procedure followed to perform timing analysis for any mixed-signal design.

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