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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 433 Documents

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512 bit-SHA3 design approach and implementation on field programmable gate arrays S. Neelima; R. Brindha
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 3: November 2019
Publisher : Institute of Advanced Engineering and Science

In this work, the authors consider the newly selected Hash Secure (SHA-3) algorithm on FPGA Gateway. The design is logically optimized for zone efficiency by combining the Rho steps and the one-pass algorithm. Logically recording these three steps registers leads to usage 16% of the logical resources for all implementations. This in turn reduces the latency and increases the maximum operating frequency of the project. It uses only 240 sections and has a frequency of 301.02 MHz compared to the design results with the previous FPGA implementation described in SHA3-512, the design shows the Throughput-Per-Slice (TPS) ratio of 30, 1.

Dynamic modeling of the birefringence effects induced in semiconductor optical amplifier for all-optical telecommunication systems A. Elyamani; A. Zatni; A. Moumen; H. Bousseta
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020
Publisher : Institute of Advanced Engineering and Science

The semiconductor optical ampliﬁers (SOA) are all-optical multifunctional devices. The improvement of their performance will, therefore, be of great importance for modern optical telecommunication systems. We propose in this article to develop a dynamic model that enables us to simulate the dynamic behavior of SOA's birefringence effects. The determination of a numerical model is a multidisciplinary activity that needs engineering skills, optimization and physics. This numerical model enables to describe the propagation of a picosecond optical pulse passing through the SOA and takes into account its polarization and the phenomenon of energy coupling between the eigenmodes of SOA (TE mode and TM mode). In this paper, we will, first of all describe the numerical algorithm of our model, and then we will propose to make a dynamic characterization of the effect of the nonlinear polarization rotation in the SOA, which will allow us to study the all-optical logic gates as well as all the other digital components based on the nonlinear effect of birefringence in SOA.

DESIGN AND PERFORMANCE IMPROVEMENT OF CNTFET BASED CONTENT ADDRESSABLE MEMORY (CAM) CELLS Hajare, Raju; C.P, Mallikarjunagowda; Deekshitha, Deekshitha; J, Madhuri.; Anaya, Anaya
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp%p

The scaling down of transistors is of paramount importance to make ICs and devices more portable and efficient. As it is the most basic component of every electronic device, there is need of finding better and innovative methods of transistor characterization. CNTFET has shown the promise and is best suited for today?s faster digital processing units and Memory devices. Here Carbon Nano Tube (CNT) is characterized for its electrical property and then designed a XOR based CAM cell using CNTFET. Both delay and power analysis for the designed CAM is done.

BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications M. Parvathi; N. Vasantha; K. Satya Prasad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

Design and Development of Texture Filtering Architecture for GPU Application Using Reconfigurable Computing Sanket Suresh Naik Dessai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

Graphical Processing Units (GPUs) have become an integral part of today’s mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. The texture filter unit is designed to process geometric data like vertices and convert these into pixels on the screen. This process involves number of operations, like circle and cube generation, rotator, and scaling. The texture filter unit is designed with all necessary hardware to deal with all the different filtering operations. The designed texture filtering units are modelled in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.Circle and cube coordinates are generated for circle and cube generation. The work can form the basis for designing a complete reconfigurable GPU.

FPGA Implementation of High Speed Hardware Efficient Carry Select Adder Saravanakumar Saravanakumar; Vijeyakumar Vijeyakumar; Sakthisudhan Sakthisudhan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction.

Decision Based Median Filter algorithm using Resource Optimized FPGA to Extract Impulse Noise Rutuja Nandkumar Kulkarni; Pradip C Bhaskar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014
Publisher : Institute of Advanced Engineering and Science

Median filter is a non-linear filter used in image processing for impulse noise removal. It finds its typical application in the situations where edges are to be preserved for higher level operations like segmentation, object recognition etc. This paper presents an accurate and efficient noise detection and filtering algorithm for impulse noise removal. The algorithm includes two stages: noise detection followed by noise filtering. The proposed algorithm replaces the noisy pixel by using median value when other pixel values, 0’s or 255’s are present in the selected window and when all the pixel values are 0’s and 255’s then the noise pixel is replaced by mean value of all the elements present in the selected window. Similarly algorithm checks for five different conditions to preserve image details, object boundary in high level of noise densities. This median filter was designed, simulated and synthesized on the Xilinx family of FPGAs (XC3S500E of Spartan-3E). The VHDL was used to design the above 2-D median filter using ISE (Xilinx) tool & tested & compared for different grayscale images.

Energy and Area Effective Hardware Design of Lifting Approach Discrete Wavelet Transform Khamees Khalaf Hasan; Ibrahim Khalil Salih; Abdumuttalib. A. Hussen
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018
Publisher : Institute of Advanced Engineering and Science

This paper presents low power Discrete Wavelet Transform DWT architecture, comprising of forward and inverse multilevel transform for 5/3 lifting scheme LS based wavelet transform filter. This LS filter consists of integer adder units and binary shifter rather than multiplier and divider units as in the convolution based filters; hence it is more adaptable to energy efficient hardware performance. The proposed architecture is described using the VHDL based methodology. This VHDL code has been simulated and synthesized to achieve the gate level building design which can be organized to be effectively developed in hardware environment. The Quartus II 9.1 software synthesis tools were employed to implement 2D-DWT VHDL codes in Altera Development board DE2, with Cyclone II FPGA device. The proposed LS wavelet architectures can be attained by focusing on the physical FPGA devices to considerably decrease the needed hardware expenditure and power consumption of the design. The utilized logic and register elements of the architecture are 127 slices (only 1%) usage from 33216 and the architecture consumes only 0.033 W. Simulations were performed using different sizes of gray scale images that authenticate the proposed design and attain a speed performance appropriate for numerous real-time applications.

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control Varatharajan Ramachandran
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 1: March 2015
Publisher : Institute of Advanced Engineering and Science

A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity, that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.

A Novel Face Recognition Algorithm Using Gabor - based KPCA Umasankar Ch; D. Naresh Kumar; Md. Abdul Rawoof; D. Khalandar Basha; N. Madhu
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018
Publisher : Institute of Advanced Engineering and Science

The Gabor wavelets are used to extract facial features, and then a doubly nonlinear mapping kernel PCA (DKPCA) is proposed to perform feature transformation and face recognition. The conventional kernel PCA nonlinearly maps an input image into a high-dimensional feature space in order to make the mapped features linearly separable. However, this method does not consider the structural characteristics of the face images, and it is difficult to determine which nonlinear mapping is more effective for face recognition. In this work, a new method of nonlinear mapping, which is performed in the original feature space, is defined. The proposed nonlinear mapping not only considers the statistical properties of the input features, but also adopts an Eigen mask to emphasize those important facial feature points The proposed algorithm is evaluated based on the Yale database, the AR database, the ORL database and the YaleB database.

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