International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
433 Documents
<![CDATA[NIOS II Based Secure Test Wrapper Design for Testing Cryptographic Algorithms ]]>
<![CDATA[Chakrapani Kannan]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i3.pp185-191
<![CDATA[Cryptographic algorithms need infrastructure for testing them against security attacks. Normally many methods are proposed for testing these cryptographic primitives. Normal designs cannot be applied to all types of cryptographic chips. Usually build in self test is applied for the intellectual property chips for testing them. But it suffers from many problems such as side channel attack, backholes, high area overhead, etc.., to overcome all these drawbacks test wrapper is designed and tested using NIOS II economy soft core processor. NIOS II is utilized as the soft core processor and cryptographic algorithms are executed. RTL view of these cryptographic circuits is described. Synthesis result shows the chip planner view of the circuits and the area required for the logic elements. NIOS II soft-core processors perform well for testing the cryptographic algorithms. Results with respects to area optimization, memory and speed are discussed. The logic components required for design using NIOS II is optimized. Memory required is also less compare to other processors. Area required is optimized using NIOS II processor and it is flexible for design of complex circuits.]]>
<![CDATA[Digitalized Electronic Voting System ]]>
<![CDATA[Dukka Bindu Venkata Raghav]]>;
<![CDATA[Sunith Kumar Bandi]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v5.i3.pp143-147
<![CDATA[In the present scenario, Electronic Voting Machines ("EVM") are being used in India, generally for state elections. These EVMs are being used since 1999 upto till date. The EVMs reduce the time for both casting a vote and declaring the results when compared to the old paper ballot systems, up to 2004 there is no Tampering and security provided for EVMs after 2004 Supreme court and Election Commission decided to introduce EVMs with Voter Verified Paper Audit Trail(VVPAT) system but it also having some difficulties like missing of names in the voter list, requirement of huge manpower, storing of EVMs for counting purpose etc, so our proposed method is useful to overcome above problems in the voting system by using the Biometric and Aadhaar information. ]]>
<![CDATA[6 Transistors and 1 memristor based memory cell ]]>
<![CDATA[Kazi Fatima Sharif]]>;
<![CDATA[Satyendra N. Biswas]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 1: March 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i1.pp42-51
<![CDATA[Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor. The proposed memory cell is very stable during successive read operates and comparatively faster and also occupies less amount of silicon area. The stability of the data during successive read operation and noise margin are in the promising range. Extensive simulation results using LTspice and Cadence software tools demonstrate the validity and competency of the proposed model.]]>
<![CDATA[IMPLEMENTED WITH DUAL MATERIAL GATE SILICON-ON- INSULATOR JUNCTIONLESS CMOS CIRCUITS ]]>
<![CDATA[Wagaj, S. C.]]>;
<![CDATA[Patil, S. C.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp%p
<![CDATA[In this research paper, we demonstrate the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). A comparison of circuit performance of the n and p channel dual material gate silicon on insulator transistor and junctionless transistor. The logic performance of a CMOS circuits is evaluated in terms of static power dissipation, output voltage v/s input voltage, propagation delay and noise margin. When metal oxide semiconductor field effect transistor (MOSFET) in saturation region gate capacitance of junctionless transistor reduces compare to with junction transistor. The circuit simulation result CMOS inverter propagation delay of junctionless transistor is reduced by 25% compare with junction transistor. DMG SOI JLT common source amplifier gives amplification of 1.25 times which is higher than DMG SOI transistor. The noise margin of junctionless CMOS inverter is 23% maximum compared to with junction CMOS inverter. NAND gate static power dissipation of DMG SOI JLT is improved by 53%, 46% and 34% compared to DMG SOI Transistor at 20nm, 30nm and 40nm channel length. On current of dual material gate junctionless transistor is increases when channel length increase compare to with junction transistor. Static power dissipation of junctionless transistor inverter is reduced by 3% compared to with junction transistor inverter at channel length 30nm.]]>
<![CDATA[ARM9-Linux Karnel ]]>
<![CDATA[Pradip Ram Selokar]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 1: March 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v5.i1.pp49-56
<![CDATA[ARM9 supports the Linux Kernel. On a development system it is advantageous to load the Root File System (RFS) through Network File System (NFS). Several pieces of software are involved to boot a linux kernel on SAM9 products. First is the ROM code which is in charge to check if a valid application is present on supported media (FLASH, DATAFLASH, NANDFLASH, and SDCARD).]]>
<![CDATA[AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key ]]>
<![CDATA[Samir El Adib]]>;
<![CDATA[Naoufal Raissouni]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v1.i2.pp67-74
<![CDATA[Advanced Encryption Standard (AES) adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and small throughput. Some companies that employ ultra-high security in their systems may look for a key size bigger than 128-bit AES. In this paper, 128, 192 and 256-bit AES hardware are implemented and compared in terms of throughput and area. The target hardware used in this paper is Virtex XC5VLX50 FPGA from Xilinx. Total area and Throughput results are presented and graphically compared.]]>
<![CDATA[Smart Assisted Vehicle for Disabled/Elderly using Raspberry Pi ]]>
<![CDATA[Shubham Pandey]]>;
<![CDATA[Shubham Chandewar]]>;
<![CDATA[Krishnamoorthy A.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 2: July 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i2.pp82-87
<![CDATA[Independent mobility is a key component in maintaining the physical and psychosocial health of an individual. Further, for people e having disabled/elderly, independent mobility increases vocational and educational opportunities, reduces dependence on caregivers and family members, and promotes feelings of self-reliance. Psychologically, a decrease in mobility can lead to feelings of emotional loss, anxiety, depression, educed self-esteem, social isolation, stress, and fear of abandonment. Even though the benefits of powered mobility are well documented, the safety issues associated with operation of powered vehicles often prevent clinicians and rehabilitation practitioners from prescribing powered mobility. So we are introducing an intelligent vehicle for disables/elderly people which uses an array of sensors to help with the movement of the vehicle with minimal human interaction. Functionalities of the proposed system are further enhanced using android interface connect to the vehicle via Bluetooth.]]>
<![CDATA[FPGA Implementation of Park-Miller Algorithm to Generate Sequence of 32-Bit Pseudo Random Key for Encryption and Decryption of Plain Text ]]>
<![CDATA[Bharatesh N]]>;
<![CDATA[Rohith S]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 3: November 2013 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v2.i3.pp99-105
<![CDATA[There are many problems arises in randomized algorithms whose solutions are fundamentally based on assumptions that pure random numbers exist, so pseudo-random number generators can imitate randomness sufficiently well for most applications. The proposed scheme is a FPGA implementation of Park-Miller Algorithm for generating sequence of Pseudo-Random keys. The properties like High speed, low power and flexibility of designed PRNG(Pseudo Random Number Generator) makes any digital circuit faster and smaller. The algorithm uses a PRNG Module, it contains 32-bit Booth Multiplier, 32-bit Floating point divider and a FSM module. After generating a sequence of 32-bit Pseudo-Random numbers we have used these numbers as a key to Encrypt 128-bit plain text to become a cipher text and by using the same key to decrypt the encrypted data to get original Plain text. The Programming is done in Verilog-HDL, successfully synthesized and implemented in XILINX Spartan 3E FPGA kit.]]>
<![CDATA[Berger Code Based Concurrent Online Self-Testing of Embedded Processors ]]>
<![CDATA[G. Prasad Acharya]]>;
<![CDATA[M. Asha Rani]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v7.i2.pp74-81
<![CDATA[In this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable methodology is proposed and integrated in 32-bit DLX Reduced Instruction Set Computer (RISC) processor on a single silicon chip. The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self- testing to detect temporary faults.]]>
<![CDATA[Implementation of LOCO-I Lossless Image Compression Algorithm for Deep Space Applications ]]>
<![CDATA[Praveena, P.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v3.i3.pp98-103
<![CDATA[Present emerging trend in space science applications is to explore and utilize the deep space. Image coding in deep space communications play vital role in deep space missions. Lossless image compression has been recommended for space science exploration missions to retain the quality of image. On-board memory and bandwidth requirement is reduced by image compression. Programmable logic like field programmable gate array (FPGA) offers an attractive solution for performance and flexibility required by real time image compression algorithms. The powerful feature of FPGA is parallel processing which allows the data to process quicker than microprocessor implementation. This paper elaborates on implementing low complexity lossless image compression algorithm coder on FPGA with minimum utilization of onboard resources for deep space applications.]]>
