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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 456 Documents
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Video saliency detection using modified high efficiency video coding and background modelling Narasimha, Sharada P.; Lingareddy, Sanjeev C.
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i2.pp431-440

Abstract

Video saliency has a profound effect on our lives with its compression efficiency and precision. There have been several types of research done on image saliency but not on video saliency. This paper proposes a modified high efficiency video coding (HEVC) algorithm with background modelling and the implication of classification into coding blocks. This solution first employs the G-picture in the fourth frame as a long-term reference and then it is quantized based on the algorithm that segregates using the background features of the image. Then coding blocks are introduced to decrease the complexity of the HEVC code, reduce time consumption and overall speed up the process of saliency. The solution is experimented upon with the dynamic human fixation 1K (DHF1K) dataset and compared with several other state-of-the-art saliency methods to showcase the reliability and efficiency of the proposed solution.
Guidance device for visually impaired people based on ultrasonic signals and open hardware Yauri, Ricardo; Alvarez, Kevin; Cotaquispe, Junior; Ynquilla, Jordy; Llerena, Oscar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 3: November 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i3.pp520-527

Abstract

Visual impairment is a complex challenge that affects people of all ages, and it is estimated that around 2.2 billion people worldwide lack adequate access to medical treatment and support. In Latin America, there is a lack of attention to people with visual disabilities, evidenced by poor urban infrastructure and lack of compliance with inclusion laws. Some projects stand out for the use of prototypes with artificial vision technology, global positioning system (GPS) and smart canes. Therefore, the objective of the project is to use ultrasonic sensors and a low-cost electronic device coupled to canes, for obstacle detection and mobility using an open hardware embedded system. The results confirmed the efficiency in the detection and operation of the ultrasonic sensor by activating the light emitting diode (LED), the buzzer and the vibrating motor according to the programmed distances. Challenges were identified, such as adapting the sensor to the tilt of the cane and the importance of accurate calibration of the ultrasonic sensor. The system met its objectives by detecting objects in a range of 2 to 50 cm and providing sound alerts to improve the perception of blind people.
Design of IoT-based monitoring system for temperature and dissolved oxygen levels in catfish aquaculture pond water Sari, Nurma; Savitri, Yuniar; Wahyono, Sri Cahyo; Santoso, Joko; Nasrulloh, Amar Vijai
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 3: November 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i3.pp687-698

Abstract

One of the fish in Indonesian waters that has been successfully bred and cultivated is the catfish (Pangasius sp.). In catfish farming, there are several water quality factors that need to be considered, such as temperature and dissolved oxygen levels. Based on the existing description, it is very important to pay attention to the water quality of aquaculture ponds, especially temperature and dissolved oxygen levels for fish survival. This study aims to create an internet of things (IoT) based monitoring system for temperature and dissolved oxygen levels in catfish aquaculture pond water based on NodeMCU ESP8266. Monitoring system is using SEN0237 gravity analog dissolved oxygen sensor, DS18B20 sensor module, NodeMCU ESP8266, 20×4-character liquid-crystal display (LCD), micro secure digital (SD) card module, internet modem. Data from measurements of temperature and dissolved oxygen levels are stored online in the Adafruit.io database in the .csv format and on a micro secure digital (SD) card in the device in the .txt format. The lowest value of dissolved oxygen levels and temperature are 3.4 mg/L or 3.4 ppm and a temperature of 27.9 °C, respectively. Meanwhile, the highest value of dissolved oxygen levels and temperature are 4.6 mg/L or 4.6 ppm and temperature of 30.9 °C, respectively.
Channel reconstruction through improvised deep learning architecture for high-speed networks Jayashanka, Parinitha; Shobha, Byrappa Nanjundaiah
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 3: November 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i3.pp786-798

Abstract

Efficient acquisition of channel state information (CSI) is quite complicated process but immensely essential to exploit probable benefits of massive multiple input multiple output (MIMO) systems. Therefore, a deep learningbased model is utilized to estimate channel feedback in a massive MIMO system. The proposed improvised deep learning-based channel estimation (IDLCE) model enhances channel reconstruction efficiency by using multiple convolutional layers and residual blocks. The proposed IDLCE model utilizes encoder network to compress CSI matrices where decoder network is used to downlink reconstruct CSI matrices. Here, an additional quantization block is incorporated to improve feedback reconstruction accuracy by reducing channel errors. A COST 2,100 model is adopted to analyse performance efficiency for both indoor and outdoor scenarios. Further, deep learning-based model is used to train thousands of parameter and correlation coefficients much faster and to minimize computational complexity. The proposed IDLCE model evaluate performance in terms of normalized mean square error (NMSE), correlation efficiency and reconstruction accuracy and compared against varied state-of-art-channel estimation techniques. Excellent performance results are obtained with large improvement in channel reconstruction accuracy
An efficient high performance reconfigurable canonical sign digit architecture for software defined radio Chalampalem, Vijaya Bhaskar; Pidugu, Munaswamy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i1.pp25-32

Abstract

Software defined radios (SDRs) are highly motivated for wireless device modelling due to their flexibility and scalability over alternative wireless design options. The evolutionary structure of finite impulse response (FIR) filters was designed for a proposed reconfigurable canonical sign digit (CSD) approach. Considering the complex trade-off, this is accomplished with many FIR taps, which is a challenging assignment. On the baseband processing side, design is given with parameterization-controlled FIR filter tap selection. Optimal processing models to overcome the reconfigurable design issues associated with the SDR system for a multi-standard wireless communication system root cosine filter standard are often used to implement multiple FIR channelization topologies, each of which is tied to a particular in-phase and quadrature (IQ) symbol. Additionally, it demonstrates the viability of using a multi-modulation baseband modulator in the SDR system for next-generation wireless communication systems to maximise adaptability with the least amount of computational complexity overhead. The proposed multiplier-less FIR filter-based reconfigurable baseband modulator, according to the experimental results, offers a 6% complexity reduction and a 47% improvement in performance efficiency over the current SDR system.
Kernel rootkit prevention model using multiclass Srinivasan, Suresh Kumar; Thalavaipillai, Sudalaimuthu
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i2.pp395-402

Abstract

Malicious individuals can access a computer network or application thanks to a series of programmes known as rootkit malware. These kernel rootkits use covert methods to conceal the kernel components, various control frameworks, and system activities, making identifying or prohibiting their presence in the target machine challenging. The bulk of rootkit detection and prevention techniques used today are particular to a system and dependent on recognized sources, making them ineffective for growing, evolving, concealed, or unnamed rootkits. This study proposes using the kernel rootkit prevention model using multiclass (KRPMM) system to identify hash values and detect/prevent such rootkits. The file downloaded by the client, who is availing of the service, is not permitted into the node used by the client in the cloud. But, it is redirected to the node wherein the file that has been downloaded and has entered the node anew is examined by a program which is specially coded to test the presence of rootkit in the file by some mechanisms and then comes to a conclusion of either the file being malicious or the file being clean and is free of rootkits. KRPMM tested only 64 rootkits.
Improved automated parallel implementation of GMM background subtraction on a multicore digital signal processor Bariko, Smail; Klilou, Abdessamad; Abounada, Abdelouahed; Arsalane, Assia
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 3: November 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i3.pp552-559

Abstract

Scene segmentation is an essential step in a wide range of video processing applications, for instance, object recognition and tracking. The Gaussian mixture model (GMM) for background subtraction (BS) has gained widespread usage in scene segmentation, despite its known computational intensity. To tackle this challenge, we propose a practical solution to accelerate processing through a parallel implementation on an embedded multicore platform. In this paper, we present an improved automated parallel implementation of the GMM algorithm using the Orphan directive provided by open multiprocessing (OpenMP). Experimental assessments conducted on the eight cores of the C6678 digital signal processor (DSP) demonstrate significant advancements in parallel efficiency, particularly when handling high-resolution frames, including high-definition (HD) and full-HD resolutions. The achieved parallel efficiency surpasses the results obtained with classical OpenMP scheduling modes, encompassing dynamic, static, and guided approaches. Specifically, the parallel efficiency reaches approximately 82% for full-HD resolution frames and, 99.3% for low-resolution frames, respectively.
Cost and performance aware scheduling technique for cloud computing environment Gorva, Santhosh Kumar; Anandachar, Latha C.
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i1.pp9-19

Abstract

Recently, lot of interest have been put forth by researchers to improve workload scheduling in cloud platform. However, execution of scientific workflow on cloud platform is time consuming and expensive. As users are charged based on hour of usage, lot of research work have been emphasized in minimizing processing time for reduction of cost. However, the processing cost can be reduced by minimizing energy consumption especially when resources are heterogeneous in nature; very limited work have been done considering optimizing cost with energy and processing time parameters together in meeting task quality of service (QoS) requirement. This paper presents cost and performance aware workload scheduling (CPA-WS) technique under heterogeneous cloud platform. This paper presents a cost optimization model through minimization of processing time and energy dissipation for execution of task. Experiments are conducted using two widely used workflow such as Inspiral and CyberShake. The outcome shows the CPA-WS significantly reduces energy, time, and cost in comparison with standard workload scheduling model.
C4O: chain-based cooperative clustering using coati optimization algorithm in WSN Singh, Preet Kamal; Singh, Harmeet; Kaur, Jaspreet
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i1.pp96-104

Abstract

In order to provide sensing services to low-powered IoT devices, wireless sensor networks (WSNs) organize specialized transducers into networks. Energy usage is one of the most important design concerns in WSN because it is very hard to replace or recharge the batteries in sensor nodes. For an energy-constrained network, the clustering technique is crucial in preserving battery life. By strategically selecting a cluster head (CH), a network's load can be balanced, resulting in decreased energy usage and extended system life. Although clustering has been predominantly used in the literature, the concept of chain-based clustering has not yet been explored. As a result, in this paper, we employ a chain-based clustering architecture for data dissemination in the network. Furthermore, for CH selection, we employ the coati optimisation algorithm, which was recently proposed and has demonstrated significant improvement over other optimization algorithms. In this method, the parameters considered for selecting the CH are energy, node density, distance, and the network’s average energy. The simulation results show tremendous improvement over the competitive cluster-based routing algorithms in the context of network lifetime, stability period (first node dead), transmission rate, and the network's power reserves.
Embedded systems as programmable square wave generator in wireless power transfer Akbar, Sabriansyah Rizqika; Setiawan, Eko; Basuki, Achmad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 3: November 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i3.pp568-576

Abstract

This study focuses on the design and development of programmable frequency generator using embedded devices that are able to produce square wave signals in the wireless power transfer (WPT) transmitter. We validate the accuracy of the output signal by measuring distance error. We validate that our system can change and sweep the frequency and produce high power by measuring the absorbed power in the load. We conduct the frequency sweep analysis to find optimal frequency and the frequency splitting phenomenon. The experiments show that the system can produce and sweep the square wave signals with less than 1% error. We also find that the frequency splitting occurred when distance among two coils in the range 0.5-6.5 cm and the splitting disappeared when the distance is above 7.5 cm. The frequency splitting shows that the measured optimum frequency differs from the calculation. The difference confirms that the programmable frequency generator is needed to adjust the frequency that can transfer maximum power to the load.

Page 37 of 46 | Total Record : 456

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