cover
Article Per Year (5 Year)
All
Home Page
OAI Link
Editorial Team
Contact
Reviewer
Google Scholar
Contact Name
-
Contact Email
-
Phone
-
Journal Mail Official
-
Editorial Address
-
Location
Kota yogyakarta,
Daerah istimewa yogyakarta
INDONESIA
International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 456 Documents
 37   38   39   40   41 
Design and implementation of smart traffic light controller with emergency vehicle detection on FPGA Mohamad Hadis, Nor Shahanim; Abdullah, Samihah; Abdul Sukor, Muhammad Ameerul Syafiqie; Hamzah, Irni Hamiza; Setumin, Samsul; Ibrahim, Mohammad Nizam; Azmin, Azwati
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp48-59

Abstract

Increased traffic volumes resulting from urbanization, industrialization, and population growth have given rise to complex issues, including congestion, accidents, and traffic violations at intersections. In the absence of a functional smart traffic light system, traffic congestion occurs due to imbalanced traffic flow at intersections. Current traffic management lacks provisions for ensuring the unobstructed movement of emergency vehicles, even a small delay for which can have significant consequences. This paper presents a smart traffic light controller developed using Verilog hardware description language (HDL) in Quartus Prime 21.1 and Questa Intel field programmable gate array (FPGA) Starter Edition 2021.2, and implemented on an Altera DE2-115 FPGA. The controller is designed specifically to detect emergency vehicle at four-way intersections for inputs radio frequency identification (RFID) readers and infrared (IR) sensors. The RFID readers and IR sensors are managed through slide switches on the FPGA board. The smart traffic light controller contains three sub-modules: clock division, counter, and finite state machine (FSM) operation, enabling it to manage traffic in scenarios with emergency vehicles, high traffic density, and low traffic density. This proposed system can alleviate intersection congestion by controlling access and allocating time effectively. In conclusion, the project ensures the smooth passage of emergency vehicles by continuously monitoring their presence and giving them priority in traffic flow.
Finite element analysis method as an alternative for furniture prototyping process and product testing Kristianto, Fesa Putra; Amarta, Zain; Hutasoit, Nicolas; Fariz, Nuthqy; Herinda, Fania Putri
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp231-242

Abstract

In the current furniture industry, making furniture goes through many steps. There are ordering materials, designing, building a prototype, and testing samples. This process is considered quite complex, requiring significant costs, and lengthy production time. The application of finite element analysis (FEA) can be a solution to simulate the furniture manufacturing process. Objective of this research was to determine FEA could substitute making and test prototype furniture thereby saving costs and time. This method utilizes ANSYS 18.1 software for more accurate and rapid calculations, incorporating load variables of 400 N, 600 N, 800 N, and 1,000 N, along with gravitational acceleration of 10 \frac{m}{s^2}. The research evaluates the difference (expressed as a percentage) between the results obtained from simulations and those obtained directly from experiments, considering maximum equivalent stress, maximum principal stress, and total deformation values. The final step involves comparing the simulation with direct testing in terms of cost and time. The research results show an average error factor of 5% across all aspect. In terms of cost, the method can save 1,807 USD and reduce production time by up to one month. From these findings, it can be concluded that the process of prototyping and sample testing can be replaced using the finite element method.
Comparative analysis of feature descriptors and classifiers for real-time object detection Nandeshwar, Vikas J.; Bhatlawande, Sarvadnya; Solanke, Anjali; Sathe, Harsh; Satao, Shivanand; Satpute, Safalya; Saste, Atharva
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp89-99

Abstract

Detecting objects within complex environments, such as urban settings, holds significant importance across various applications, including driver assistance systems, traffic monitoring, and obstacle detection systems. Particularly crucial for these applications is the accurate differentiation between cars and roads. This study introduces a novel approach that leverages traditional feature descriptors and classifiers for real-time object detection. It conducts an exhaustive comparative analysis of feature descriptors and classifiers to identify the most effective model for real-time object detection. Handcrafted features of images are extracted using algorithms such as scale invariant feature transform (SIFT), oriented fast and brief (ORB), fast retina key-point (FREAK), and local binary pattern (LBP). Seven classifiers are employed, including support vector machine (SVM), K-nearest neighbors (KNN), random forest (RF), decision tree (DT), logistic regression (LR), Naive Bayes, and extreme gradient boosting (XGBoost). The performance of the 28 generated combinations of feature descriptors and classifiers is evaluated based on the parameters of accuracy, precision, F1 score, and recall. The model utilizing LBP and XGBoost achieves the highest accuracy, reaching 83.59%. The system architecture comprises a camera, a high-speed computing unit, a display, and an audio subsystem, with the algorithm implemented on a Raspberry Pi 4B (8 GB).
Comparative analysis of ZigBee, LoRa, and NB-IoT in a smart building: advantages, limitations, and integration possibilities Inthasuth, Tanakorn; Kaewjumras, Yongyut; Somwong, Sahapong; Boonsong, Wasana
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp165-175

Abstract

This paper compares the performance of various wireless technologies: ZigBee, long range (LoRa), and narrowband internet of things (NB-IoT), which support smart building applications. The highlight of this work is that we focus on wireless communication between the floors of the building by analyzing the performance metrics using the received signal strength indicator (RSSI) and packet loss ratio (PLR). First, the ZigBee tests confirmed reliable packet delivery without any loss over distances up to 40 meters on the same floor, with RSSI results ranging from -65.5 to -87.5 dBm. ZigBee also maintained signal transmission through one cross-floor level, with RSSI values between -60 and -119 dBm. The second set of tests, with LoRa, indicated signal transmission over several floors with slightly improved RSSI values for the 2 dBi antenna compared to those for the -4 dBi antenna, despite increased packet loss with distance. Finally, NB-IoT showed the most consistent long-range connectivity, achieving a stable signal up to 458 meters from the base station with RSSI levels varying from -55.6 to -74.6 dBm, without packet loss in all tests. This study demonstrates how such technologies could be used in smart buildings and provides suggestions on how to determine the most suitable systems and configure them to ensure reliable communication networks within the building.
Artificial intelligence driven robotic control system for personalized elderly care and foot massage Bhatlawande, Shripad; Shilaskar, Swati; Akotkar, Soham; Joshi, Anish; Ansari, Zayd
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp35-47

Abstract

This research presents an electronic system for providing foot massage to the elderly, along with artificial intelligence (AI) driven voice-controlled conversation bot. The problem under study focuses on the elderly age group suffering from foot related ailments, most commonly foot pain. Also, the risk of depression or anxiety is high for this age group due to social isolation. These problems are addressed by the system under discussion integrated with a voice assistant to converse with the elderly. The AI assisted conversation bot enables the elderly to make customized reminders for their timely medications and provides general updates on essential topics. The system extends to provide the elderly, foot, and calf massage controlled with mobile application. It consists of a low power motor arrangement along with a high computing system. The electronic system was subjected to trials on elderly for verification and validation of the system to assess its ability of providing users with appropriate assistance. The trials were conducted on twenty elderly, aged sixty, and above, living self-sufficiently with foot related ailment. All elderly were subjected to the conversation bot along with the foot and calves’ massage, providing subjective feedback on the system's ability to enhance their quality of life. The subjective feedback after quantification have demonstrated the ability of the system in improving their living standards.
A fast half-subtractor using 8T static random access memory for in-memory computation Prabhakar, Deepika; Shylashree, Nagaraja; Narasimhaiah, Sunitha Yariyur; Mariswamappa, Yashaswini Biligere; Hemaraj, Sheetal Singrihalli
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp273-281

Abstract

The existing system for computation completely incorporates Von-Neumann architecture which has limitations with respect to its memory, parallelism and power constraints. This has affected the efficiency of the computing system. Novel architectural solutions are required to meet the growing demands for improved computational efficiency and power management in very large scale integration (VLSI) systems. To deal with the large-scale data, computation in memory (CIM) has been introduced. The paper presents the half subtractor circuit and the In-memory computation co-design using eight transistors static random access memory (SRAM) cell whose read circuitry is transmission gate based. The proposed half-subtractor with the CIM is implementation is carried out in 180 nm complementary metal– oxide–semiconductor (CMOS) technology. The sensing scheme used is the latch-based sense amplifier along with the 8T SRAM cell. The proposed SRAM with transmission-gate based read circuitry along with latch-based sense amplifier reduces the delay and power consumed during the read operation significantly and a bit reduction during the write operation. The static noise margin (SNM) for read operation has been increased by 9% in the transmission gate-based SRAM as compared to conventional 8T SRAM. The delay of the proposed design has been reduced by 53% during the read operation and 4.43% during the write operation. The power consumed has been reduced by 3% and 8.6% during read and write operations, respectively.
Algorithm-driven development of a simulation tool for industrial manipulator stability analysis Mustary, Shabnom; Kashem, Mohammod Abul; Chowdhury, Mohammad Asaduzzaman; Uddin, Jia
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp69-78

Abstract

Industrial manipulators are essential to many manufacturing processes because they increase efficiency and productivity dramatically. However, maintaining operational safety and averting potential risks in industrial environments requires that these manipulators be stable. The development and implementation of an entirely algorithm-driven novel simulation tool intended to assess industrial manipulators’ stability in-depth are presented in this research. The suggested tool combines sophisticated mathematical models with the material properties of the manipulator, such as deflection, stiffness, and damping. To analyses the dynamic behaviour of manipulators under various operating situations, a hypothetical simulation technique to assess the stability of robot manipulators combined with material properties is taken into consideration. The simulation tool offers vital insights into the stability characteristics of manipulators, allowing engineers and designers to enhance their performance and guarantee operational safety. The simulation tool’s usefulness is showcased through case studies and comparative evaluations, emphasizing its capacity to improve the design and implementation of industrial manipulators in practical situations. In summary, this research enhances the field of industrial automation by offering a strong framework for assessing and upgrading the stability of manipulator systems. This, in turn, improves productivity and safety in industrial settings.
Performance analysis of parallel prefix adders developed with field programmable gate array technology Mahammad, Masood Ahmad; Uppala, Appala Raju; Prasad, Suggala Ram; Marouthu, Anusha
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp109-116

Abstract

In many digital systems like high-performance computing and digital signal processing, parallel prefix adders are vital. Field programmable gate array (FPGA) technology is a well-known platform for developing parallel prefix adders. FPGA performance depends on bit size of the adder, the adder structure chosen, and the implementation specifications. An examination of the performance and area of parallel prefix adders developed using FPGA technology is presented in this research work. We look into how different design factors, such as the adder structure and the number of input bits, affect the performance and area of parallel prefix adders. The different adders used are Sklansky, Kogge-Stone, Brent-Kung, Han-Carlson, and Ladner-Fisher adders. These adders are implemented using Verilog hardware description language (Verilog HDL) on FPGA boards. The performance is significantly influenced by choice of adder structure and design factors optimized for area or performance. The suggestions for choosing the best adder structure and design factors for the best performance or optimized area are obtained from the synthesis results. Ladner-Fisher adders is best parallel prefix adder with respect area and performance compared with the Sklansky, Kogge-Stone, Brent-Kung and Han-Carlson. Our synthesis can be used as a guide for designers looking to construct specific hardware on FPGA.
Design of flood warning prototype using ESP32 module-based ultrasonic sensors Hasibuan, Arnawan; Zahiri, Muhtadi; Jannah, Misbahul; Roid, Fahrian; Almunadiansyah, Rizky; Abta, Armen; Nrartha, I Made Ari
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp126-135

Abstract

Natural disasters such as floods can cause many losses to humans, such as material losses, trauma for the victims, and loss of life. Floods that occur can be caused by various factors such as human activity itself which results in changes in natural spatial planning, so the arrival of floods is also difficult to detect with certainty. Based on this, it is necessary to develop a technological innovation that helps provide a warning of the arrival of a natural disaster. The ESP32 microcontroller is one of the technologies that can be used to create an early warning system for the arrival of floods. The design and manufacture of this technology certainly involves modeling, algorithm planning, assembly of the components of the tools used, including wiring and mechanics as needed. This tool uses an internet of things (IoT) system with the help of an ESP32 microcontroller that supports integration via Wi-Fi and Bluetooth so that it can be connected to a smartphone device as a notification receiver in real time and accurately by notifying the water level which will be an indicator of potential flooding, so that people are more alert in the face of flooding to prevent and minimize the losses that will be experienced.
Low-noise amplifier with pre-distortion architecture for ultra-wide band application in radio frequency Siddanna, Pradeep Kumar; Divakarachari, Parameshachari Bidare
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp208-220

Abstract

Ultra-wide band (UWB) is a wireless technology deployed for transmitting data at high rates over short distances. Similar to Wi-Fi and Bluetooth, UWB is a radio frequency (RF) technology that operates via radio waves. To remove minor noise and glitches, low noise amplifier (LNA) is required because it amplifies weak signals without significantly adding noise. However, UWB has multiple frequencies that require coefficient change due to frequency variations. When low-pass filter (LPF) is employed to solve this, updates are necessary to manage delay and power because the LPF feedback is connected to LNA to increase delay and power consumption. In this research, LNA with a pre-distortion architecture is proposed to remove minor noises and small glitches. It is processed by using pre-distortion as an active component which reduces delay and power consumption in UWB. The pre-distortion process operates in the subthreshold voltage range by providing a transistor to each frequency as input, inturn effectively reducing the noise. The proposed LNA with pre-distortion architecture is developed on 180-nm complementary metal-oxide semiconductor (CMOS) technology using Cadense ASIC tool. The proposed architecture achieves a noise figure (NF) of 2.16 dB and less power consumption of 43.06×10-6 W when compared to the existing techniques namely, cascade amplifiers, W-band LNA, reflectionless receiver (RX), and broadband RF receiver front-end circuits.

Page 39 of 46 | Total Record : 456

 37   38   39   40   41 

Filter by Year

2012 2025


Reset
Filter By Issues
All Issue Vol 14, No 3: November 2025 Vol 14, No 2: July 2025 Vol 14, No 1: March 2025 Vol 13, No 3: November 2024 Vol 13, No 2: July 2024 Vol 13, No 1: March 2024 Vol 12, No 3: November 2023 Vol 12, No 2: July 2023 Vol 12, No 1: March 2023 Vol 11, No 2: July 2022 Vol 11, No 1: March 2022 Vol 10, No 3: November 2021 Vol 10, No 2: July 2021 Vol 10, No 1: March 2021 Vol 9, No 3: November 2020 Vol 9, No 2: July 2020 Vol 9, No 1: March 2020 Vol 8, No 3: November 2019 Vol 8, No 2: July 2019 Vol 8, No 1: March 2019 Vol 7, No 3: November 2018 Vol 7, No 2: July 2018 Vol 7, No 1: March 2018 Vol 6, No 3: November 2017 Vol 6, No 2: July 2017 Vol 6, No 1: March 2017 Vol 5, No 3: November 2016 Vol 5, No 2: July 2016 Vol 5, No 1: March 2016 Vol 4, No 3: November 2015 Vol 4, No 2: July 2015 Vol 4, No 1: March 2015 Vol 3, No 3: November 2014 Vol 3, No 2: July 2014 Vol 3, No 1: March 2014 Vol 2, No 3: November 2013 Vol 2, No 2: July 2013 Vol 2, No 1: March 2013 Vol 1, No 3: November 2012 Vol 1, No 2: July 2012 Vol 1, No 1: March 2012 More Issue