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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 433 Documents

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Design of a 60 GHz power amplifier in a 45nm CMOS Rashmi S. B.; Siva S. Yellampalli
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

This Paper presents a design and implementation of class-AB power amplifier which works at 60GHz unlicensed frequency band. This power amplifier uses a MOSFET from gpdk45 technology library. The design simulation is done by cadence Analog Design Environment. This proposed power amplifier yields a power added efficiency of 23.45% and a power gain S21 of 10dB at 60GHz. The output impedance of proposed power amplifier is needs to be matched with 73Ω antenna impedance. The S22 output matching of the simulated power amplifier is -18dB at 60GHz. The input side is matched to arbitrary impedance of 50Ω the resulting S11 of simulated result is noted to be -15dB at 60GHz. The proposed circuit has a noise figure of 3.85dB. The proposed circuit has a Pout-1dB of 8.5dBm. the designed class AB power amplifier is an important component in 60GHz transceiver. The layout of the associated circuit is drawn with the total size of 0.107um2.

FPGA Synthesis of Reconfigurable Modules for FIR Filter Saranya R; Pradeep C; Neena Baby; Radhakrishnan R
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 2: July 2015
Publisher : Institute of Advanced Engineering and Science

Reconfigurable computing for DSP remains an active area to explore as the need for incorporation with more conventional DSP technologies turn out to be obvious. Conventionally, the majority of the work in the area of reconfigurable computing is aimed on fine grained FPGA devices. Over the years, the focus is shifted from bit level granularity to a coarse grained composition. FIR filter remains and persist to be an important building block in various DSP systems. It computes the output by multiplying input samples with a set of coefficients followed by addition. Here multipliers and adders are modeled using the concept of divide and conquer. For developing a reconfiguarble FIR filter, different tap filters are designed as separate reconfigurable modules. Furthermore, there is an additional concern for making the system fault tolerant. A fault detection mechanism is introduced to detect the faults based on the nature of operands. The reconfigurable modules are structurally modeled in Verilog HDL and simulated and synthesized using Xilinx ISE 14.2. A comparison of the device utilization of reconfigurable modules is also presented in this paper by implementing the design on various Virtex FPGA devices.

Comparison analysis of three value logic 8T CNTFET SRAM Cell with 6 CMOS SRAM CELL at 32nm technology S.Tamil Selvan
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019
Publisher : Institute of Advanced Engineering and Science

This paper proposed a new concept of highly SNM and low power SRAM cell using carbon nanotube FETs (CNTFETs) at 18nm technology node. As device physical gate length is reduced to below 65 nm, device non-idealities such as large parameter variations and exponential increase in Dynamic leakage current make the I-V characteristics substantially different from traditional MOSFETs and become a serious obstacle to scale devices. CNFETs have received widespread attention as one of the promising successor to MOSFETs. The proposed circuit was simulated in HSPICE using 32nm Stanford CNFET model. Analysis of the results shows that the proposed CNTFET based 3VL 8T SRAM cell, power dissipation, and stability substantially improved compared with the conventional CMOS 6T SRAM cell by 51% and 58% respectively at the expense of 4% write delay increase.

Low Cost Microcontroller Based Automatic Billing System with Protective Shielding from RF Waves Suganthi Evangeline
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 2: July 2016
Publisher : Institute of Advanced Engineering and Science

Shopping Mall is a complex of shops representing various merchandisers that enables the customers to buy all their needed things. As it is easier for people to come and buy all their things in a common place, shopping malls are crowded. As people are coming in large numbers to buy the groceries and house hold products for the full month, the billing counters are flooded with people. In order to avoid such large queues at the billing counter, we are coming up with Smart Cart using newly evolved RFID Technology. In our proposed method, the bill is automatically generated in the trolley as the customer purchases the product.

A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor Pritty Pritty; Manoj Kumar; Mariyam Zunairah
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 3: November 2019
Publisher : Institute of Advanced Engineering and Science

Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.

Quadcopter based emergency medikit delivery system for hill stations C. R. Balamurugan; S. M. Revathy; P. Vijayakumar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp201-212

Nowadays UAV’s are more common for search, rescue and surveillance. A quadcopter UAV system is proposed to be used for aerial transportation of medicine. A Quadcopter has a drive chassis having a propeller, ESC, motor, frames and battery. The quadcopter is supported with GPS to know the exact position. To know the exact location and delivering medicine to accident area, an audio and video system is used. The quad frame built from quality materials, which are reinforced and much more stronger, this reduces arm breakage. A set of two plastic propellers, one normal and one pusher (reverse) to rotate and lift up the quadcopter. The brushless out-runner will provide more power with its high efficiency, long run times. The ESC includes programmable motor braking, soft start for helicopters and planes, timing, throttle input range and low-voltage cutoff. Lithium-Polymer (Li-Po) battery for very lightweight, small size and durability without losing charging capacity. The whole quadcopter process can be monitored and controlled by a remote control system, quadcopter will capture the live video and current status can be seen visualized and provides information about all the other exact conditions in real-time.

TWO STAGE 10-BIT ADC WITH DELAY-LINE TDC BASED SECOND STAGE Mattada, Mahantesh; Guhilot, Hansraj
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 3: November 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v9.i3.pp%p

Two stage Time based 10-bit ADC is designed and verified in a commercial VLSI CAD tool. Simple VCO based ADC design used in the first stage as coarse, whereas TDC based second stage used for fine conversion. Each stage will give 5bit resolution and work concurrently during the conversion process. Delay-line/Flash TDC is used in the second stage because of its better conversion speed. Flash TDC will give thermometer code and a binary conversion stage is required. To make it simple and area efficient, ROM based Thermometer to Binary(T2B) converters are used in the final readout module. Average power dissipation of 1.155mW for overall system is measured and makes it suitable for low power applications.

FPGA based Implementation of Symmetrical Reduced Switch Multilevel Inverter K. Venkataramanan; B. Shanthi; T. S. Sivakumaran
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017
Publisher : Institute of Advanced Engineering and Science

Multilevel inverter has become more popular and attractive for drive applications. Among the various modulation techniques, Carrier based techniques has been commonly used because of their simplicity and flexibility. This paper presents the comparisons of bipolar multicarrier pulse width modulation for the new symmetrical multilevel inverter. The performance parameters of new multilevel inverter were analyzed through various switching strategies. The detailed study has been carried out by MATLAB/SIMULINK. The real time implementation was carried out using FPGA. The results of both simulation and experimentation were compared.

Design and Development of Stream Processor Architecture for GPU Application Using Reconfigurable Computing Sanket Dessai; Krishna Bhushan Vutukuru
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013
Publisher : Institute of Advanced Engineering and Science

Graphical Processing Units (GPUs) have become an integral part of today’s mainstream computing systems. They are also being used as reprogrammable General Purpose GPUs (GP-GPUs) to perform complex scientific computations. Reconfigurability is an attractive approach to embedded systems allowing hardware level modification. Hence, there is a high demand for GPU designs based on reconfigurable hardware. Stream processor consists of clusters of functional units which provide a bandwidth hierarchy, supporting hundreds of arithmetic units. The arithmetic cluster units are designed to exploit instruction level parallelism and subword parallelism within a cluster and data parallelism across the clusters.For decreasing the area and power, a single controller is used to control data flow between clusters and between host processor and GPU. The designed of stream processor unit has been carried out in Verilog on Altera Quartus II and simulated using ModelSim tools. The functionality of the modelled blocks is verified using test inputs in the simulator.The simulated execution time of 8-bit pipelined multiplier is 60 ps and 100 ns for 8-bit pipelined adder while operating at 90 MHz.

MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN Ramesh Pawase; N.P. Futane
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 2: July 2017
Publisher : Institute of Advanced Engineering and Science

Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization. The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware.

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