Garuda - Garba Rujukan Digital

Article Per Year (5 Year)

All

International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
Website

Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 456 Documents

6 7 8 9 10

Metal-Embedded SU-8 Slab Techniques for Low-Resistance Micromachined Inductors Manot Mapato; Prapong Klysuban; Thanatchai Kulworawanichpong; Nimit Chomnawang
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 2: July 2017
Publisher : Institute of Advanced Engineering and Science

This work presents new fabrication technique for micro power-inductors by using metal-embedded SU-8 slab techniques. This techniques used X-ray lithography to fabricate high aspect-ratio LIGA-like micro-structures in form of embedded structure in SU-8 slab and applied for inductor’s winding fabrication with aspect-ratio of 10. Thishigh-aspect ratiostructure can provide very low resistance winding but preserve small form factor and low profile. Inductors were designed as pot-core structures with8 μm-thick permalloy core and 250 μm-thick copper winding. 4-types of inductors were fabricated including 3, 5, 10 and 16 turns in the area of 1.8 mm2 to 9.5 mm2. All inductors have overall heights of 370 μm, measured inductance value in a range of 70 nH to 1.3 μH at 1 MHz and DC resistance value of 30 mΩ to 336 mΩ for 3 turns to 16 turns respectively. From this result, high aspect-ratio inductors show good results including low-resistance, high inductance, and a small form factor as expected.

Implementation of Video Capture and Playback in Mobile Systems Sanket Dessai; K Ramakrishna
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 3: November 2013
Publisher : Institute of Advanced Engineering and Science

Mobile phones are backbone of the mobile communications and have experienced fastest growing segment in the consumer market. In the 3G and 4G mobiles, video recording is an essential entertainment features so the user can record and play the video within the mobile phone. In this paper, video capture and playback implementation had been carried out by integrating the camera module to the GSM phone. An alaysis of the video processing had been carried out. Image sensor and LCD module had been interfaced with the base band processor through the video processor. To interface the different module necessary PCB schematic diagram had been arrived. Software implementation had been carried out for the Human Machine Interface for various settings of the camera module, which is integrated with the video processor. The developed playback system had been tested for the various senerious. In this video has been captured through the camera sensor and at the time of playback measured the resolution, power consumption and image transfer rates of the various modules used in the developed camera phone.

FPGA Implementation of DTCWT and PCA Based Watermarking Technique M. S. Sudha; T. C. Thanuja
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018
Publisher : Institute of Advanced Engineering and Science

The hardware implementation of the image watermarking algorithm offers numerous distinct advantages over the software implementation in terms of low power consumption, less area usage and reliability. The advantages of Dual Tree Complex Wavelet Transform (DTCWT) and Principle Component Analysis (PCA) techniques are extracted to improve the robustness and perceptibility. The hardware watermarking solution is more economical, because adding the component only takes up a small dedicated area of silicon. The algorithm is developed and simulated using Matlab, Simulink and system generator. The implementation is carried out using Spartan 6 Diligent Atlys Field Programmable Gate array (FPGA). The architecture uses 256 slice registers, 257 slice Look Up Tables (LUT’s) and 47 I/O pins. It also meets the requirement of high speed architecture with a delay of 1.328ns and an operating frequency of 549.451MHz.

Bilinear Interpolation Image Scaling Processor for VLSI Architecure Pawar Ashwini Dilip; K Rameshbabu; Kanase Prajakta Ashok; Shital Arjun Shivdas
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCU)is invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process.

Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems Manoj Kumar Vishnoi; Satya Sai Srikant
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018
Publisher : Institute of Advanced Engineering and Science

This paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response.

Application of New Approach of design flow for Hardware/Software Embedded System with the Use of Design Patterns in Fuzzy control system Ali Bouyahya; Yassine Manai; Joseph Haggège
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 2: July 2015
Publisher : Institute of Advanced Engineering and Science

This paper present a new method of conception of hardware/software embedded system design methodology based on use of design pattern approach called Abstract_factory. We called this new design tool “smart cell”. The main idea of the conception of embedded systems design is based on the used of object-oriented design ULM2.0. When the smart-cell is implemented, we justify their uses as a design tool that allows, first, to develop a specified application of fuzzy controller called PDC (parallel distributed conpensation). Second, the specification of the generation phases of the system architecture design, and eventually partitioning the application on heterogeneous platform based on hardware resource DSP and FPGA software to illustrate the proposed approach.

VLSI Design and Comparison of DA and LMS Based Reconfigurable FIR Filter P. Hemanthkumar; Y. Sai Kiran; V. Nava Teja
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 2: July 2016
Publisher : Institute of Advanced Engineering and Science

Here, we exhibit the design optimization of one- and two-dimensional fully-pipelined computing structures for area-delay-power-efficient implementation of finite impulse response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. This plan is found to offer a flexible choice of the address length of the look-up-tables (LUT) for DA-based computation to determine suitable area-time trade-off. It is seen that by using smaller address-lengths for DA-based computing units, it is possible to decrease the memory-size but on the other side that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density and energy throughput are estimated for different filter orders and address-lengths. Obtained results on analysis shows that performance metrics of the proposed implementation is broadly in line with theoretical expectations. We have seen that the choice of address-length M=4 gives the best of area-delay power-efficient realizations of the FIR filter for different filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.

Two state-of-the-arts current-mode ternary full adders based on CNTFET Technology Mona Moradi
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 1: March 2020
Publisher : Institute of Advanced Engineering and Science

Adder core respecting to its various applications in VLSI circuits and systems is considered as the most critical building block in microprocessors, digital signal processors and arithmetic operations. Novel designs of a low power and complexity Current Mode 1-bit Full Adder cell based on CNTFET technology has been presented in this paper. Three major parts construct their structures; 1) the first part that converts current to voltage; 2) threshold detectors (TD); and 3) parallel paths to convey the output currents flow. Adjusting threshold voltages which are significant factor for setting threshold detectors switching point has been achieved by means of CNTFET technology. It would bring significant improvements in adjusting threshold voltages, regarding to its unique characterizations. Simple design, less transistor counts and static power dissipation and better performance comparing previous designs could be considered as some advantages of the novel designs.

Design and analysis of different full adder cells using new technologies Nandhaiahgari Dinesh Kumar; Rajendra Prasad Somineni; CH Raja Kumari
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020
Publisher : Institute of Advanced Engineering and Science

CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.

An Automated Way of Baking Process for Moisture Sensitive Components A. Ramamoorthy; M. Jagadeeshraja; L. Manivannan; K. Raja
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 1: March 2016
Publisher : Institute of Advanced Engineering and Science

The objective of my project is to the new technology termed as “baking process” to remove the moisture content available in the particular electronics devices which is used in Rea time industrial application. In Industries there are certain policies are maintained for semiconductor devices, which referred as “Shelf life” of the material. Once it crossed its lifetime, some process need to done to extend this. Depends on the moisture sensitive characteristics baking is employed mainly to shelf life extension. The Baking is the process of removing of moisture content from particular semiconductor device in order to effective usage in the production line. In my propose method the moisture content is measured by corresponding moisture sensor. If it is normal level the processor goes to the normal state, If it is reaches the abnormal level (presence of moisture) the processor baked the product. Temperature and humidity sensors are effectively monitor and provide the signal to the processor. The UTLP kit provide the information about the status of the product.

Page 8 of 46 | Total Record : 456

6 7 8 9 10

Filter by Year

2012 2025

Filter By Issues

All Issue Vol 14, No 3: November 2025 Vol 14, No 2: July 2025 Vol 14, No 1: March 2025 Vol 13, No 3: November 2024 Vol 13, No 2: July 2024 Vol 13, No 1: March 2024 Vol 12, No 3: November 2023 Vol 12, No 2: July 2023 Vol 12, No 1: March 2023 Vol 11, No 2: July 2022 Vol 11, No 1: March 2022 Vol 10, No 3: November 2021 Vol 10, No 2: July 2021 Vol 10, No 1: March 2021 Vol 9, No 3: November 2020 Vol 9, No 2: July 2020 Vol 9, No 1: March 2020 Vol 8, No 3: November 2019 Vol 8, No 2: July 2019 Vol 8, No 1: March 2019 Vol 7, No 3: November 2018 Vol 7, No 2: July 2018 Vol 7, No 1: March 2018 Vol 6, No 3: November 2017 Vol 6, No 2: July 2017 Vol 6, No 1: March 2017 Vol 5, No 3: November 2016 Vol 5, No 2: July 2016 Vol 5, No 1: March 2016 Vol 4, No 3: November 2015 Vol 4, No 2: July 2015 Vol 4, No 1: March 2015 Vol 3, No 3: November 2014 Vol 3, No 2: July 2014 Vol 3, No 1: March 2014 Vol 2, No 3: November 2013 Vol 2, No 2: July 2013 Vol 2, No 1: March 2013 Vol 1, No 3: November 2012 Vol 1, No 2: July 2012 Vol 1, No 1: March 2012 More Issue

Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name
-

Contact Email
-

Phone
-

Journal Mail Official
-

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Home Page

OAI Link

Editorial Team

Contact

Reviewer

Google Scholar

Contact Name -

Contact Email -

Phone -

Journal Mail Official -

Editorial Address -

Location Kota yogyakarta, Daerah istimewa yogyakarta INDONESIA

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Contact Name
-

Contact Email
-

Phone
-

Journal Mail Official
-

Editorial Address
-

Location
Kota yogyakarta,

Daerah istimewa yogyakarta

INDONESIA