International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
456 Documents
<![CDATA[FPGA Based a PWM Technique for Permanent Magnet AC Motor Drives ]]>
<![CDATA[Tole Sutikno]]>;
<![CDATA[Nik Rumzi Nik Idris]]>;
<![CDATA[Nuryono Satya Widodo]]>;
<![CDATA[Auzani Jidin]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v1.i2.pp43-48
<![CDATA[The permanent magnet AC motor trapezoidal (BLDC motor) is not strictly DC motor, which uses a pulsed DC fed to the stator field windings to create a rotating magnetic field. Therefore, the motor needs an electronic commutation to provide the rotating field. A pair of switches must be turned on sequentially in the correct order to energize a pair of windings. If the incorrect order is applied, then the BLDC motor will not operate properly. This paper presents a smart guideline to ensure that the order to energize a pair of windings is correct. To ensure the guideline, FPGA based a simple commutation state machine scheme to control BLDC motor is presented. The experiment results have shown that the guideline is correct. The commutation scheme was successfully realized using Altera's APEX20KE FPGA to control BLDC motor in both of forward/reverse rotations or forward/reverse regenerative braking properly.]]>
<![CDATA[Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator ]]>
<![CDATA[Sanket Dessai]]>;
<![CDATA[Sandeep G.]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v7.i1.pp21-33
<![CDATA[This paper focus on design and develop a Hardware Accelerator which can plug in to Universal Serial Bus of any modern low power low cost embedded development system to do complex processing in a plug and play development environment. Cryptographic algorithms, steganography and encoding decoding applications can use co-devices to accelerate performance. In this paper an implementation of a hardware infrastructure for computing though USB bus of any small scale embedded controller board. Execution engine of the accelerator will be an FPGA which is connected to a USB controller with DDR memory to store user data. FPGAs can perform the process faster than low power microcontrollers to solve such algorithms. For the implementation XILINX ARTIX 7 FPGA is used to off load the algorithm for faster processing. System also has a Cypress USB interface chip for offloading data path. Hardware also has a DRAM memory for dumping the data to be stored. Design also explores different futuristic features like interrupt connection for faster response path, shared memory architecture for hand shake mechanism and GPIO connection for implementation of faster interfaces for IO expansion.]]>
<![CDATA[CO Pollution Warning System for Indoor Parking Area Using FPGA ]]>
<![CDATA[Prima Dewi Purnamasari]]>;
<![CDATA[Evan G. Sumbayak]]>;
<![CDATA[Vicky Dwi Kurniawan]]>;
<![CDATA[RR. Wulan Apriliyanti]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v2.i2.pp64-75
<![CDATA[From some compounds used as parameters in air pollution-such as O3, Particulate Materials, CO, NO2, SO2 and Pb-CO is the most common cause of poisoning accidents. Indoor parking area is one sample of potential area for CO pollution. However, according to the scientific nature of CO-tasteless, colorless, and odorless-people exposed to CO are usually not aware that s/he exposed to dangerous levels of CO. This research aimed to make a prototype of an embedded system that can monitor air pollution, give an effective warning and it should be affordable. The prototype of CO air pollution alert system has been successfully built using FPGA Xilinx Spartan 3E as the major component. Sensor Hanwei MQ7 used in this prototype has been tested in a simulation box using cigarette smoke as CO pollutant and the reading result has met the characteristic curve in the datasheet. The system interface has met user satisfaction with MOS value 4.31 from 5 scales. Based on the response time testing, we conclude that FPGA is suitable to be used in a system that performs fast parallel processing based on logical actions from the input given.]]>
<![CDATA[FPGA implementation of DS-CDMA Transmitter and Receiver ]]>
<![CDATA[Harinath Mandalapu]]>;
<![CDATA[B Murali Krishna]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 3: November 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i3.pp179-185
<![CDATA[Direct sequence spread Spectrum (DSSS) is also known as direct sequence code division multiplexing. In direct sequence spread spectrum the stream of information to be transmitted is divided into small pieces each of which is allocated across to a frequency channel across the spectrum. Data signal at the point of transmission is collaborated with a higher data-rate bit sequence (also called chipping code) that divides the data according to a spreading ratio. A redundant chipping code helps the signal resist interference and also enables the original data to be recovered if data bits are damaged during the transmitting. In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented on SPARTAN 3E FPGA. The Xilinx synthesis technology (XST) of Xilinx ISE tool used for synthesis of transmitter and receiver on FPGA Spartan 3E.]]>
<![CDATA[Design and Implementation of Adaptive FIR filter using Systolic Architecture ]]>
<![CDATA[Ravi H Bailmare]]>;
<![CDATA[S.J. Honale]]>;
<![CDATA[Pravin V Kinge]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v3.i2.pp54-61
<![CDATA[The tremendous growth of computer and Internet technology wants a data to be process with a high speed and in a powerful manner. In such complex environment, the conventional methods of performing multiplications are not suitable to obtain the perfect solution. To obtain perfect solution parallel computing is use in contradiction. The DLMS adaptive algorithm minimizes approximately the mean square error by recursively altering the weight vector at each sampling instance. In order to obtain minimum mean square error and updated value of weight vector effectively, systolic architecture is used. Systolic architecture is an arrangement of processor where data flows synchronously across array element. This project demonstrates an effective design for adaptive filter using Systolic architecture for DLMS algorithm, synthesized and simulated on Xilinx ISE Project navigator tool in very high speed integrated circuit hardware description language (VHDL) and Field Programmable Gate Arrays (FPGAs). Here, by combining the concept of pipelining and parallel processing in to the systolic architecture the computing speed increases.]]>
<![CDATA[Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology ]]>
<![CDATA[T. Kanthi]]>;
<![CDATA[D. Sharath Babu Rao]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v7.i3.pp149-156
<![CDATA[This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.]]>
<![CDATA[Design of Secure Transmission of Multimedia Data Using SRTP on Linux Platform ]]>
<![CDATA[Shashidhar H.G.]]>;
<![CDATA[Sanket Dessai]]>;
<![CDATA[Shilpa Chaudhari]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 2: July 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i2.pp71-81
<![CDATA[This paper aims for providing a viable solution for security in streaming media technology. Service providers do not want the end users to capture and duplicate streaming media data. Once captured data can be re-distributed to millions without any control from the source. Licensing issues also dictate the number of times end user may utilize the data. Encryption is not sufficient as it leaves the system vulnerable to duplication and recording after decryption. In this paper an attempt has been made to transmit digital multimedia data to multiple users. The transmission of the video/audio data has been attempted from one PC to another PC. While doing this, security considerations have to be taken care by using suitable encryption/decryption techniques. A research carried out on the different data transmission protocols reveals that the Secure Real Time Transport Protocol (SRTP) is one of the best available protocols. Hence the SRTP has been deployed in this project on Linux OS using socket programming. The code for the transmitter and the receiver is designed and developed around the SRTP library for transmission of multimedia data. The solution is illustrated by choosing an example of a video clip for transmission and reception. This model increasing the security of streaming media and adds a measure of integrity protection, but it is primarily intended to aid in replay preventions.]]>
<![CDATA[Neuronal logic gates realization using CSD algorithm ]]>
<![CDATA[Lakshmi kiran Mukkara]]>;
<![CDATA[K.Venkata Ramanaiah]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v8.i2.pp145-150
<![CDATA[Any digital circuit is made with fundamental building blocks i.e. logic gates. Artificial neural networks (ANN) became an emerging area in various applications such as prediction problems, pattern recognition, and robotics and system identification due to its processing capabilities with parallel architecture. Realization of Boolean logic with neural networks is referred as neuronal logic. ANN computes faster as it requires of low and simple precision computations. Also, it requires economic and low precision hardware. Neural network contains more number of addition and multiplication processes. It is known that CSD algorithm computes faster than conventional or standard multipliers. In this paper, VLSI implementation of neuronal half adder with CSD algorithm is proposed and implemented in FPGA. The results are compared with that of conventional and vedic multiplier. It is observed that CSD algorithm provides lowest delay and low power consumption in comparison with vedic algorithm and conventional method but at the expense of minimum area.]]>
<![CDATA[Web Based Home Security and Automation System ]]>
<![CDATA[Norfadzlia Mohd Yusof]]>;
<![CDATA[Aiman Zakwan Jidin]]>;
<![CDATA[Lim Mei Sze]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 2: July 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v5.i2.pp90-95
<![CDATA[Home security and automation is crucial issue concerned by people. A home security system is needed for convenience and safety. A home automation system is a key to having effective energy efficiency in the house. In this paper, we present the design and implementation of a web-based home security and automation system. This system make use of PIR motion sensor to detect intruder in the house. This sensor is further fed to microcontroller which would help the GSM module to send notification to house owner regarding the intrusion. On the other hand, the LDR light sensor is used to provide auto-light functionality which will turn on the light at night and dim it at day time. A web-based system function as a remote control system for user to monitor control the sensors and lights at home in order to save energy consumption. This system is accessible by user anytime and anywhere as long there is an Internet connection.]]>
<![CDATA[Designing ALU using GDI method ]]>
<![CDATA[Mohammadreza Fadaei]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 3: November 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v8.i3.pp151-161
<![CDATA[As CMOS technology is continuously becoming smaller and smaller in nanoscale regimes, and circuit resistance to changes in the process for the design of the circuit is a major obstacle. Storage elements such as memory and flip-flops are particularly vulnerable to the change process. Power consumption is also another challenge in today's Digital IC Design. In modern processors, there are a large number of transistors, more than a billion transistors, which increases the temperature and the breakdown of its performance. Therefore, circuit design with low power consumption is a critical need for integrated circuits today. In this study, we deal with GDI techniques for designing logic and arithmetic circuits. We show that this logic in addition to low power consumption has little complexity so that arithmetic and logic circuits can be implemented with fewer transistors. Various circuits such as adders, differentiation and multiplexers, etc. have been designed and implemented using these techniques, and published in various articles. In this study, we review and evaluate the advantages and disadvantages of these circuits.]]>
