International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
456 Documents
<![CDATA[Application of optimal artificial intelligence based tuned controllers to a class of embedded nonlinear power system ]]>
<![CDATA[Magdy A. S. Aboelela]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 1: March 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i1.pp83-92
<![CDATA[This paper studies the implementation of the Bat Inspired Algorithm (BIA) as an optimization technique to find the optimal parameters of two classes of controllers. The first is the classical Proportional-Integral-Derivative (PID). The second is the hybrid fractional order and Brain Emotional Intelligent controller. The two controllers have been implemented, separately, for the load frequency control of a single area electric power system with three physical imbedded nonlinearities. The first nonlinearity represents the generation’s rate constraint (GRC). The second is owing to the governor dead band (GDB). The last is due to the time delay imposed by the governor-turbine link, the thermodynamic process, and the communication channels. These nonlinearities have been embedded in the simulation model of the system under study. Matlab/Simulink software has been applied to obtain the results of applying the two classes of controllers which have been, optimally, tuned using the BIA. The Integral of Square Error (ISE) criterion has been selected as an element of the objective function along with the percentage overshoot and settling time for the optimum tuning technique of the two controllers. The simulation results show that when using the hybrid fractional order and Brain Emotional Intelligent controller, it gives better response and performance indices than the conventional Proportional-Integral-Derivative (PID) controllers.]]>
<![CDATA[A Novel High Speed FPGA Architecture for FIR Filter Design ]]>
<![CDATA[Sachin B. Jadhav]]>;
<![CDATA[Nikhil Niwas Mane]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 1: March 2012 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v1.i1.pp1-10
<![CDATA[This paper presents the details of hardware implementation of linear phase FIR filter using merged MAC architecture. Speed of convolution operation of FIR filter is improved using merged MAC architecture. By exploiting the reduced complexity made possible by the use of sparse powers of two partial products terms coefficients, an FIR filter tap can be implemented with 2B full adders, and 2B latches, where B is intermediate wordlegnth. Word and bit level parallelism allows high sampling rates, limited only by the full adder delay. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication and accumulation operation by minimizing the number of combinational gates using higher n: 2 compressors, which is required more for Array multiplier at the time of implementation of array architecture. This novel architecture allows the implementation of high sampling rate filters of significant length on FPGA Spartan-3 device (XC3S400 PQ-208). The simulation result shows convolution output of digital FIR filter which is done using Questa Sim 6.4c Mentor Graphics tool. The experimental test of the proposed digital FIR filter is done using Spartan-3 device (XC3S400 PQ-208)]]>
<![CDATA[Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm ]]>
<![CDATA[G. Vadiraj]]>;
<![CDATA[K. Shivanand]]>;
<![CDATA[B. Sampat]]>;
<![CDATA[G. Subramanya Nayak]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i1.pp36-40
<![CDATA[Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.]]>
<![CDATA[Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication ]]>
<![CDATA[Sachin B. Jadhav]]>;
<![CDATA[Jayamala K. Patil]]>;
<![CDATA[Ramesh T. Patil]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 1: March 2013 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v2.i1.pp15-20
<![CDATA[This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.]]>
<![CDATA[Thermal Analysis of Fair Scheduling in Real-time Embedded Systems ]]>
<![CDATA[Tayyaba Bokhari]]>;
<![CDATA[Sajjad Haider Shami]]>;
<![CDATA[Farhan Haseeb]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 1: March 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v7.i1.pp48-56
<![CDATA[Over the past few decades, increased demand of highly sophisticated real-time applications with complex functionalities has directly led to exponentially increased power consumption and significantly elevated system temperatures. These elevated temperature and thermal variations present formidable challenges towards system reliability, performance, cooling cost and leakages. This article explores the thermal management strength of two fairness based algorithms, namely Proportional Fair (PFair) and Deadline Partitioning Fair (DP-Fair). In related literature, the introduction of fairness is often considered as a tool to achieve optimality in multiprocessor scheduling algorithms. This work shows that these algorithms bring about better thermal profile when compared with the commonly used Earliest Deadline First (EDF) algorithm in similar conditions both in uniprocessor and multiprocessor environments. A simulation is conducted for periodic task set model. The obtained results are encouraging and show that use of fairness based algorithms reduces the operating temperature, peak temperature, and thermal variations.]]>
<![CDATA[Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing ]]>
<![CDATA[Anshuman Sharma]]>;
<![CDATA[Abdul Hafeez Syed]]>;
<![CDATA[Midhun M]]>;
<![CDATA[M R Raghavendra]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v3.i1.pp18-24
<![CDATA[This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and were implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for a data rate from 1kbps to 8kbps was implemented.]]>
<![CDATA[FPGA implementation of new LM-SPIHT colored image compression with reduced complexity and low memory requirement compatible for 5G ]]>
<![CDATA[Yasmine M. Tabra]]>;
<![CDATA[Bayan Mahdi Sabbar]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v8.i1.pp1-13
<![CDATA[The revolution in 5G mobile systems require changes to how image is handled. These changes are represented by the required processing time, the amount of space for uploading and downloading. In this paper, a development on WT (Wavelet Transform) along with LM-SPIHT (Listless-Modified Set Partitioning in Hierarchical tree) coding and with additional level of Runlength encoding for image compression has been proposed. The new implementation reduces the amount of data needed to be stored in several stages, also the amount of time required for processing. The compression has been implemented using VHDL (Very High Descriptive Language) on netFPGA-1G-CLM Kintex-7 board. The new implementation results show a reduction in the complexity as processing time.]]>
<![CDATA[The Experimental Platform Design for NCS Based on CAN Bus ]]>
<![CDATA[Zhao Weiquan]]>;
<![CDATA[Yuan Huaqiang]]>;
<![CDATA[Wei Xiaorui]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 1: March 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i1.pp22-27
<![CDATA[In order to facilitate research on the performance of Networked Control System, overcome the defects of unable to reflect the system performance, based on the CAN bus a kind of NCS experimental platform is designed. The system is composed of a main node and several slave nodes and Dc motor as the actuator. The master node is designed with ARM + U-boot + Linux structure, connecting with PC via Ethernet. For this experiment platform, using c + + Builder a scheduling algorithm performance testing software is developed, to further research on the effects of different scheduling algorithm on the NCS performance.]]>
<![CDATA[Low power and high performance FFT with different radices ]]>
<![CDATA[Md. Zakir Hussain]]>;
<![CDATA[Kazi Nikhat Parvin]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v8.i2.pp99-106
<![CDATA[FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.]]>
<![CDATA[Dynamic Partial Reconfiguration with FIR Filter Application ]]>
<![CDATA[Noopur Astik]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i3.pp201-208
<![CDATA[Dynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of Field Programmable Gate Array (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presented]]>
