International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
433 Documents
<![CDATA[Implementation of High Speed Self Switching Frequency Agile RADAR ]]>
<![CDATA[K Jansi Lakshmi]]>;
<![CDATA[K Surya Narayana Reddy]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 1: March 2014 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v3.i1.pp11-17
<![CDATA[The radar has to resist diversified jamming; High Speed self-adaptive frequency agility is an important and effective function for radars to resist jamming. The procedure to achieve this function are described, and the function is realized with FPGA using Hardware description Language, the validity is proved by on- line sampling and simulation. The High speed self-adaptive frequency agility module can analyze the type of jamming to select transmitting frequency to avoid the frequencies which have interference, under frequency diversity and fixed frequency, respectively. The general application on a searching radar shows that the module has good real-time and anti- jamming capacity.]]>
<![CDATA[An Optimal Design of CMOS Two Stage Comparator Circuit using Swarm Intelligence Technique ]]>
<![CDATA[Sasikumar Sasikumar]]>;
<![CDATA[Muthaiah Muthaiah]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v7.i3.pp131-137
<![CDATA[A swarm intelligent based optimization technique named as Flower pollination algorithm (FPA) is applied for the design of the CMOS two stage comparator circuit. The basic idea of FPA mimics the flower pollination process of flowering plants. The input control parameters of FPA improve the exploration and exploitation capabilities of optimization problem. This paper presents the design of a CMOS two-stage comparator circuit using simulation based model called swarm intelligence technique. Simulation results shows that the proposed method is capable to determine the transistor sizes and bias current values of the CMOS comparator. The results obtained from the FPA improved the design performance of comparator in terms of power consumption, MOS transistor area and gain. To investigate the efficiency of proposed approach, comparisons have been carried out with differential evolution (DE) and harmony search (HS) algorithm based circuit design. The performances of FPA based comparator design are better than the previously reported works]]>
<![CDATA[Software Design and Development of Beverage Vending Machine System Using ARM Architecture with LPC2148 ]]>
<![CDATA[Sanket Suresh Naik Dessai]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 1: March 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i1.pp13-21
<![CDATA[Beverage vending machine systems are becoming popular in the Indian market.These systems are today available in Indian MNCs and some top rated restaurants and hotels.In most systems the operation are carried manually by the operator in which the billing and change making is carried out by the owner who runnig the shop or restaurant.In India tea and coffee habits were cultured by the colonial rule of the British and the Portuguese,even tody the colonial rule had been over but the habits of tea and coffee beverage consumptions becomes as the routine daily life.Hence there is a need to understand beverage vending machine systems to serve the Indian Market. In this paper,a critical analysis of requirement has been carried out and the system design had been arrived at.The system requirement demand an ARM based controller for better system performance.To meet the system performance criteria and richest of peripherals an LPC2148 with low cost had been selected.The system is more efficient to analyse the change making and the identification had been carried out using the motors,LCDs,water heater,solenoid valve,money box,change making and dispensing unit. The system is tested and validated for the specified test cases.The milk motor run for 10 rotations to drive 200 milligrams of milk powder to the container to make to tea or coffee beverage.In this system a stepper motor had been used can be replaced by using dc motors to avaoid power losses.In future an ATM or credit card based payment system can be incorporated to these systems.]]>
<![CDATA[Integration testing based on indirect interaction for embedded system ]]>
<![CDATA[Muhammad Iqbal Hossain]]>;
<![CDATA[Woo Jin Lee]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 2: July 2019 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v8.i2.pp86-98
<![CDATA[Embedded systems comprise several modules that exchange data by interacting among themselves. Exchanging wrong resource data among modules may lead to execution errors or anomalies. Interacting resources produce dependencies between two modules where any change of resources by one module affects the functionality of another module. Several investigations of the embedded system such as aerospace or automobile system show interaction faults between modules are one of the major cause of critical software failures. Therefore, interaction testing is an essential phase to reduce the interaction faults and minimize the risk. The direct and indirect interaction between modules generates interaction faults where indirect interaction is made underneath the interface in which data dependence relationship with resources may cause a different outcome. We investigate errors based on the indirect interaction between modules and introduce a new test criterion for finding errors detectable by existing approaches in unit level but not in integration level. In this paper, we propose a noble approach to generate an interaction model using indirect interaction pattern and design test criteria based on different interaction errors to generate test cases. Finally, we use fault injection and data flow coverage techniques to evaluate the feasibility and effectiveness of our approach]]>
<![CDATA[An Efficient approach for Design and Testing of FPGA Programming using LabVIEW ]]>
<![CDATA[Naresh Kumar Reddy]]>;
<![CDATA[N. Suresh]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i3.pp192-200
<![CDATA[Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise.FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.]]>
<![CDATA[Design and Development of ARM based Electronic Test Evaluation System for RTO ]]>
<![CDATA[Shweta Salokhe]]>;
<![CDATA[U. L. Bombale]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v5.i3.pp148-152
<![CDATA[Electronic test evaluation system for driving license is very useful now a days, as there is increase in the human intervention in the system. This system make the driving license procedure transparent to human being. The proposed technological solution is advancement towards the automation of system and improves the driving test accuracy. As a contribution to society this system reduces the number of road accidents occurs due to untrained drivers.]]>
<![CDATA[A compact model of transconductance and drain conductance for DMG-GC-DOT cylindrical gate MOSFET ]]>
<![CDATA[Hind Jaafar]]>;
<![CDATA[Abdellah Aouaj]]>;
<![CDATA[Benjamin Iñiguez]]>;
<![CDATA[Ahmed Bouziane]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 1: March 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i1.pp34-41
<![CDATA[A compact model for dual-material gate graded-channel and dual-oxide thickness with two dielectric constant different cylindrical gate (DMG-GC-DOTTDCD) MOSFET was investigated in terms of transconductance, drain conductance and capacitance. Short channel effects are modeled with simple expressions, and incorporated into the core of the model (at the drain current). The design effectiveness of DMG-GC-DOTTDCD was monitored in comparing with the DMG-GC-DOT transistor, the effect of variations of technology parameters, was presented in terms of gate polarization and drain polarization. The results indicate that the DMG-GC-DOTTDCD devices have characteristics higher than the DMG-GC-DOT MOSFET. To validate the proposed model, we used the results obtained from the simulation of the device with the SILVACO-ATLAS-TCAD software.]]>
<![CDATA[A hardware system with ARM-based data processing for nano satellites ]]>
<![CDATA[Adrián Stacul]]>;
<![CDATA[Daniel Pastafiglia]]>;
<![CDATA[Ariel Di Giovanni]]>;
<![CDATA[Martín Morales]]>;
<![CDATA[Sergio Saluzzi]]>;
<![CDATA[Gerardo García]]>;
<![CDATA[Agustín Gadea]]>;
<![CDATA[Ramiro Puga]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp102-108
<![CDATA[The Institute of Scientific and Technical Research for Defense in Argentina (Instituto de Investigaciones Científicas y Técnicas para la Defensa - CITEDEF) is developing a processing hardware module based on a ARM Cortex M4 processor from STMicroelectronics. The microcontroller (MCU) has the capacity to run at a maximum clock frequency of 180 MHz, integrates a Floating Point Unit (FPU). An 8MB SDRAM was included for dynamic data allocation. This hardware will host and process the algorithms to calculate and determine the nanosatellite’s attitude. The module is intended to be Cubesat compatible, possess a flexible design, handles various inertial sensors and can manage backups on microSD memory cards with sizes up to 32GB.]]>
<![CDATA[HW SW Co-design of Adaptive Task Scheduler for Real Time Systems ]]>
<![CDATA[Dinesh G Harkut]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 1: March 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v5.i1.pp57-68
<![CDATA[In embedded system, a real-time operating system (RTOs) is often used to structure the application code and ensure that the deadlines are met by reacting on events in the environment by executing the functions within precise time. Most embedded systems are bound to real-time constraints with determinism and latency as a critical metrics. Generally RTOs are implemented in software, which in turns increases computational overheads, jitter and memory footprint which can be reduced even if not remove completely by utilizing latest FPGA technology, which enables the implementation of a full featured and flexible hardware based RTOs. Scheduling algorithms play an important role in the design of real-time systems. This paper proposes the novel FIS based adaptive hardware task scheduler for multiprocessor systems that minimizes the processor time for scheduling activity which uses fuzzy logic to model the uncertainty at first stage along with adaptive framework that uses feedback which allows processors share of task running on multiprocessor to be controlled dynamically at runtime. This Fuzzy logic based adaptive hardware scheduler breakthroughs the limit of the number of total task and thus improves efficiency of the entire real-time system. The increased computation overheads resulted from proposed model can be compensated by exploiting the parallelism of the hardware as being migrated to FPGA]]>
<![CDATA[Queued-Stack Dataflow Processing Element for a Cognitive Sensor Platform ]]>
<![CDATA[Mark McDermott]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v1.i3.pp75-86
<![CDATA[This paper describes a Queued-Stack (QS) Dataflow Processing Element (DPE) that is used in a cognitive sensor platform. The queued-stack is used for buffering input data to the DPE and for storage of variables and results. The queuing mechanism and dataflow protocol provides the capability to compose multi-node computational systems where communication between elements is via non-blocking FIFO channels. System composition is achieved using synchronous dataflow tools such as SDF3 or Ptolemy. The dataflow-processing element is implemented using single cycle micro-coded engine where the ratio of datapath transistors to control logic is optimized for programmable energy-performance sensitive applications.]]>
