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International Journal of Reconfigurable and Embedded Systems (IJRES)

IJRES
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Published by Institute of Advanced Engineering and Science

ISSN : 20894864 EISSN : 27222608 DOI : -

Core Subject : Economy,

Economics, Econometrics & Finance

The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.

Arjuna Subject : -

Articles 456 Documents

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Hardware Implementation of Intrusion Detection System for Ad-Hoc Network Reji Mano; P.C. Kishore Raja; Christeena Joseph; Radhika Baskar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016
Publisher : Institute of Advanced Engineering and Science

New technologies have been developed in wireless adhoc network need more security. To widespread the adhoc networks we turn in the attention of wireless hand held device mobile phones communicate with short distance using wireless lan card or Bluetooth. The performance of mobile phone are improved greatly for last few years .so security is more important for mobile networks In this paper hardware implementation of single hop ad-hoc network is implemented and analysed using microcontroller. The protocol implemented in this paper is primarily based on, Ad hoc On-Demand Distance Vector routing. We adopt On Demand Distance Vector routing solely based on source routing and “On Demand” process, so each packet does not have to transmit any periodic routing information. We implemented intrusion detection system with five different nodes and the performance parameters like packet delivery ratio, throughput, delay are computed with attacker and without attacker and on demand distance vector routing protocols is proposed to implement in hardware using Zigbee

Low power 11T adder comparator design C.M.R. Prabhu; Tan Wee Xin Wilson; T. Bhuvaneswari
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 1: March 2020
Publisher : Institute of Advanced Engineering and Science

Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.

Data ecryption based on multi-order FrFT, and FPGA implementation of DES algorithm A. Rabie; Kh. El Shafie; A. Hammuoda; M. Rohiem
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020
Publisher : Institute of Advanced Engineering and Science

Cryptography techniques need some algorithms for encryption of data. Most of available encryption techniques are used for textual data; a few of encryption methods are used for multimedia data; However, This Algorithms that are used for textual data may not be inefficient for multimedia, because it is size is greater than the text. Therefore, Cryptosystems need to find and develop a new encryption schemes for such data. The most popular symmetric key algorithms are Data Encryption Standard (DES). However, DES is may be not suitable for multimedia because it consumes times. Encryption and decryption of these data require different methods. In this paper a method for encryption/decryption data by using the nature of FrFT in signals analysis, based on multi-order Fractional Fourier Transform has been introduced. The security of the method used in the encryption work was taken into account to identify the different indicators to measure the security of the encryption Techniques. These indicators are: sensitivity proposed Techniques for the key, the complexity of the processes, and statistical analysis. The key is formed by combination of order of Fractional Fourier Transform. The encrypted data is obtained by the summation of different orders. Numerical simulation results are given to demonstrate this proposed method.

Survey on Performance and Energy consumption of Fault Tolerance in Network on Chip B. Naresh Kumar Reddy; Vasantha M.H; Nithin Kumar Y.B.
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 1: March 2016
Publisher : Institute of Advanced Engineering and Science

Network on Chip (NoC) is a communication subsystem, which has the logic for sending and receiving the data from different sources in a single IC, is adopting the technology of VLSI making it to be as compact as possible. However, the increasing probability of failures in NoC’s has been raising concern among the researchers due to large scale integration of components. In specific the issues of fault-tolerance, increase in length of global wires of NoC has to be addressed for on chip and multi core architectures. This survey presents a perspective on existing NoC Fault-tolerant algorithm and a Corresponding distributed fault analysis strategy that encourages in observing the fault status of individual NoC components and their adjacent communication links. The analysis of the Fault-tolerant Network subjected to dynamic workloads for large scale applications is also equally important. This research paper mainly emphasizes on Fault tolerant NoC strategies summarizing over thirty research papers.

Digital Control of Static Var Compensator with Field Programmable Gate Array Ram Shankarrao Dhekekar; N. V. Srikanth
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 3: November 2012
Publisher : Institute of Advanced Engineering and Science

This paper is about real time simulation and implementation of FPGA Digital Control of Static VAR compensator for 750km lab model of artificial transmission line. In this paper, a new method of controlling SVC using Field Programmable Gate Array (FPGA) is suggested. FPGA controller is used to generate the firing pulses required to for Static Var Compensator. Pulses are synchronized with AC input; the delay of pulses determines the firing angle to driver circuit. The proposed control scheme has been realized using XILINX FPGA SPARTAN 2 XC2S200 and tested actual testing proves that these devices when installed, they keep the bus voltage same as reference voltage (sending-end voltage). The results are prominent and give a way for real-time implementation of the proposed control schemes. These control schemes are simulated for the real-time control along with real-time modeling and simulations.The results are prominent and give a way for real-time implementation

CMOS Active Inductor Based Voltage Controlled Oscillator Dhara P Patel; Shruti Oza; Rajesh A Thakker
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 2: July 2017
Publisher : Institute of Advanced Engineering and Science

A Tunable Active Inductor (TAI) based Voltage Controlled Oscillator (VCO) for Radio Frequency (RF) applications ranging from 670 MHz - 1.53 GHz is presented. A design of low phase noise and compact VCO is proposed. In order to lower the phase noise of VCO, its RF output power has been improved. The use of low voltage active in-ductor circuit reduces the power dissipation of VCO. The single ended CMOS active inductors with minimum number of transistors are used to consume less die area of VCO circuit. The low power dissipation of the circuit have high efficiency to generate output RF power. A supply independent variable current source tunes the VCO. The post layout design is simulated in Cadence spectreRF using TSMC 180 nm process libraries. The VCO circuit shows the phase noise variation from -124 to - 126 dBc/Hz and an active area of 0.0049 mm2. The VCO core circuit, excluding output buffers, consumes 10 mW at 1.8 V supply voltage.

An Efficient Implementation of the Entire Transforms in the H.264/AVC Encoder using VHDL Farhad Rad; Ali Broumandnia
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 3: November 2013
Publisher : Institute of Advanced Engineering and Science

The H.264/AVC standard achieves remarkable higher compression performance than the previous MPEG and H.26X standards. One of the computationally intensive units in the MPEG and H.26X video coding families is the Discrete Cosine Transform (DCT). In this paper, we propose an efficient implementation of the DCT, inverse DCTs and the Hadamard transforms in the H.264/AVC encoder using VHDL. The synthesis results indicate that our implementation of the entire transforms achieves lower power, delay and area consumption compared to the existing architectures in the H.264/AVC encoder.

Impacts of Embedded Generation on Distribution Network Behavior Puladasu Sudhakar; Sushama Malaji; B. Sarvesh
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018
Publisher : Institute of Advanced Engineering and Science

This paper explores the impacts of multiple embedded generators penetration on distribution system behavior. For this rationale, a IEEE-13 bus distribution feeder was modeled and investigates by assimilating different types of embedded generation (EG) sources. Different scenarios were implemented in which WIND, SOFC FUEL CELL, SOLAR and MICRO TURBINE plants were modeled with high variability of load and generation to observe their impacts on system’s protection, unsymmetrical faults also consider observing impacts effectively. To eradicate the impacts on distribution system with presence of EG’s and distribution system undergone in the event of faults, in this paper primarily reverse power due to EG integration is estimated and sensed with reverse power relay, Further two types of Superconducting Fault Current Limiters Passive resonance CB (PRCB) SFCL and Inverse current injection CB (I-CB are proposed and results are compared for amended solution in mitigating fault current magnitude and over voltages, Finally penetrations levels are computed mathematically and All the modeling and simulations were carried out using MATLAB SIMULINK tool.

Design of AES Pipelined Architecture for Image Encryption/Decryption Module Pravin V. Kinge; S.J. Honale; C.M. Bobade
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 3: November 2014
Publisher : Institute of Advanced Engineering and Science

The relentless growth of Internet and communication technologies has made the extensive use of images unavoidable. The specific characteristics of image like high transmission rate with limited bandwidth, redundancy, bulk capacity and correlation among pixels makes standard algorithms not suitable for image encryption. In order to overcome these limitations for real time applications, design of new algorithms that require less computational power while preserving a sufficient level of security has always been a subject of interest. Here Advanced Encryption Standard (AES),as the most widely used encryption algorithm in many security applications. AES standard has different key size variants, where longer bit keys provide more secure ciphered text output. The available AES algorithm is used for data and it is also suitable for image encryption and decryption to protect the confidential image from an unauthorized access. This project proposes a method in which the image data is an input to Pipelined AES algorithm through Textio, to obtain the encrypted image. and the encrypted image is the input to Pipelined AES Decryption to get the original image. This project proposed to implement the 128,192 & 256 bit Pipelined AES algorithm for image encryption and decryption, also to compare the latency , efficiency, security, frequency & throughput . The proposed work will be synthesized and simulated on FPGA family of Xilink ISE 13.2 and Modelsim tool respectively in Very high speed integrated circuit Hardware Description Language.

Design and Implementation of a New Architecture of a Real-Time Reconfigurable Digital Modulator (DM) Into QPSK, 8-PSK, and 16-PSK on FPGA Walder Andre; Olivier Couillard
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 3: November 2018
Publisher : Institute of Advanced Engineering and Science

One of the prerequisites of Electronic Warfare (EW) is to have the means to provide secure point-to-point wireless data and voice communications with other ground stations. New technologies are giving rise to bigger information security threats. This situation illustrates the best the urgency of reducing the development and upgrade time of EW systems. Previous works suggest that digital systems are the best candidates for this purpose and therefore form the backbone of modern Electronic Warfare. Indeed, Digital Modulation (DM) techniques are widely used in modern wireless communication systems. This is largely due to their high resistance to noise and their high transmission capacity that can be achieved through data multiplexing. In this article, a new reconfigurable architecture of a Phase Shift Keying (PSK) modulation is described. The latter can be configured in real time to produce the following modulation schemes: QPSK, 8-PSK, and 16-PSK without having to regenerate the FPGA configuration bits. This action can be done by software via programming or manually using a DIP switch. The proposed design is implemented on the Xilinx xc7k325tfbg900 FPGA using the Genesis 2 development board. The Vivado Physical Design Automation tool indicates a power consumption of 303 mW by the on-chip circuit. The experimental results are in agreement with the simulations.

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