International Journal of Reconfigurable and Embedded Systems (IJRES)
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Articles
456 Documents
<![CDATA[Development of BSP for ARM9 Evaluation Board ]]>
<![CDATA[Vinayak Pandit K.]]>;
<![CDATA[Sanket Dessai]]>;
<![CDATA[Shilpa Chaudhari]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 4, No 3: November 2015 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v4.i3.pp161-172
<![CDATA[With an increasing usage of ARM9 core for different kinds of applications ranging from data acquisition to Mobile application, there arises the need for developing ARM9 based board. To bring up this board, board supporting package (BSP) is must. Board supporting package virtualizes the platform hardware so that the different drivers can be ported easily on any hardware. The boot loader is the initial stage of firmware, which initializes the hardware components presents on the board. A universal Bootloader is chosen and is to be customized with respect to target board. In the later section bootloader is interfaced to the kernel which is obtained form an authorized distributor under general purpose license. The customized board specific routines as well drivers are ported onto the hardware. Then the compiled kernel image is ported onto the target board using a debugger and SAM-BA utility. Linux kernel has seen major releases; the basic architecture of the Linux kernel has remained more or less unchanged. The latest 2.6 version of Linux kernel is ported onto target hardware. Kernel support for many architectures and high-end I/O devices gives the independence to choose appropriate hardware for developing system. The bootloader customization is the critical step, which involves a lot of modifications in the header files. BSP components such as bootloader, kernel is compiled using GNU tool chain; obtained image is ported on target using debugger. BSP porting is a very complex task, which required knowledge of hardware and software control sequence and boot strategy of the controller.]]>
<![CDATA[Design and Implementation of 8x8 Multiplier using 4-2 Compressor and 5-2 Compressor ]]>
<![CDATA[K. Hari Kishore]]>;
<![CDATA[K. Akhil]]>;
<![CDATA[G. Viswanath]]>;
<![CDATA[N. Pavan Kumar]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 3: November 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v5.i3.pp127-131
<![CDATA[In this paper, a 8x8 multiplier is realized by using 4-2 and 5-2 compressors. Low-power high speed 4-2 compressors and 5-2 compressors are extensively utilized for numerical realizations. Both the compressors circuits that is the 4-2 compressor circuit and 5-2 compressor circuit internally consist of the logic gates i.e. the XOR and XNOR gates. 4-2 compressor circuit has been designed uses a brand new partial-product reduction format that consecutively reduces the utmost output new style of number needs less variety of MOSFET’s compared to Wallace Tree Multipliers. The 4-2 compressor used is created from high-speed and consists of logic gates XOR and XNOR gates and transmission gate primarily based electronic device. The regular delay and switching energy also called as power-delay product (PDP) is differentiated with the 5-2 compressor enforced with 4-2 Compressors and while not compressors, and is evidenced to own minimum delay and PDP. Simulations are performed by mistreatment Xilinx ten.1 ISE.]]>
<![CDATA[A compact graphene based nano-antenna for communication in nano-network ]]>
<![CDATA[M. Saravanan]]>;
<![CDATA[V.R. Prakash]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 1: March 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i1.pp12-18
<![CDATA[Due to recent advances in nanotechnology, the use of nano-devices and its network becomes more popular in the field of medical, commercial and military applications. One of the major issues in designing nano-network is miniaturization of nano-devices which are limited due to communication antenna used in that device and its power constraints. At 1000nm size, an antenna resonates at around 100 THz which suffers from greater propagation loss and provides signal coverage of micrometer distances. Hence there is a need for nano-antenna with reduced size and also operating at mid infrared frequencies to provide a good signal coverage. In this paper, graphene-based nano-antenna is presented. The model resonates at 55THz frequency with a peak gain of 5.47 dB in the propagation direction. The model exploits the principle of surface plasma polarition waves for miniaturization and achieves 50% size reduction when compared to conventional nano-antenna and best suitable for nano-network communications.]]>
<![CDATA[A system verilog approach for verification of memory controller ]]>
<![CDATA[Sowmya K B]]>;
<![CDATA[Gagana P]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 2: July 2020 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v9.i2.pp153-157
<![CDATA[Memory performance has become the major bottleneck to improve the overall performance of the computer system. By using memory controller, there is effective control of data between processor and memory. In this paper, a memory controller for interfacing Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint random verification environment is built for the designed memory controller. Verification plays an important role in any design flow as it is done before silicon development. It is done at time of product development for quality checking and bug fixing in design.]]>
<![CDATA[Design and Analysis of CMOS and Adiabatic 1:16 Multiplexer and 16:1 Demultiplexer ]]>
<![CDATA[K. Anitha]]>;
<![CDATA[R. Jayachira]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 1: March 2016 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v5.i1.pp8-17
<![CDATA[Conventional CMOS is compared with two adiabatic logic styles namely Efficient Charge Recovery Logic (ECRL) and Improved Efficient Charge Recovery Logic (IECCRL). A 16:1 multiplexer and 1:16 demultiplexer using these design techniques are designed and results are compared based on their minimum/maximum power consumption and transistor count. The proposed schematics multiplexer and demultiplexer are simulated using Microwind2 and DSCH2 software.]]>
<![CDATA[Vehicle Accident Automatic Detection and Remote Alarm Device ]]>
<![CDATA[Varsha Goud]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 1, No 2: July 2012 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v1.i2.pp49-54
<![CDATA[The Rapid growth of technology and infrastructure has made our lives more easy . The advent of technology has also increased the traffic hazards and the road accident take place frequently which causes huge loss of life and property because of the poor emergency facilities. Our project will provide an optimum solution to this draw back. An accelerometer can be used in a car alarm application so that dangerous driving can be detected . It can be used as a crash or rollover detector of the vehicle during and after a crash. With signals from an accelerometer, a severe accident can be recognized. According to this project when a vehicle meets with an accident immediately Vibration sensor will detect the signal or if a car rolls over, an Micro electro mechanical system(MEMS) sensor will detects the signal and sends it to ARM controller. Microcontroller sends the alert message through the GSM MODEM including the location to police control room or a rescue team. So the police can immediately trace the location through the GPS MODEM, after receiving the information. Then after conforming the location necessary action will be taken. If the person meets with a small accident or if there is no serious threat to anyone`s life, then the alert message can be terminated by the driver by a switch provided in order to avoid wasting the valuable time of the medical rescue team. This paper is useful in detecting the accident precisely by means of both vibration sensor and Micro electro Mechanical system(MEMS) or accelerometer. As there is a scope for improvement and as a future implementation we can add a wireless webcam for capturing the images which will help in providing driver`s assistance. Keywords - Accident ,Automatic Detection, Micro electro Mechanical system , Remote Alarm Device, Vehicle]]>
<![CDATA[FPGA Based Symmetrical Multi Level Inverter with Reduced Gate Driver Circuits ]]>
<![CDATA[G. Durga Prasad]]>;
<![CDATA[V Jegathesan]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 1: March 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i1.pp53-68
<![CDATA[Multilevel converters tender advantages in terms of the output waveform quality due to the increased number of levels used in the output voltage modulation and have been widely accepted for high-power high-voltage applications. This paper introduces topology in multilevel dc link inverter (MLDCLI), which can significantly reduce the switch count and improve the performance. The preferred topology provides a dc voltage with the shape of a staircase approximating the rectified shape of a commanded sinusoidal wave, to the bridge inverter, which in turn gives the required alternating waveform. This topology requires fewer components compared to traditional Multi level Inverters (MLI).Therefore, the overall cost and complexity are significantly reduced particularly for higher output voltage levels. Finally, Matlab/Simulink and XILINX are used as a simulation and compiler architecture of control circuit embedded in FPGA. Simulation and experimental results for fifteen-level inverter are presented for validation.]]>
<![CDATA[Design of Mesh and Torus Topologies for Network-On-Chip Application ]]>
<![CDATA[Sonal S. Bhople]]>;
<![CDATA[M. A. Gaikwad]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v2.i2.pp76-82
<![CDATA[Network-on-Chip (NoC) is a general purpose on-chip communication concept that offers high throughput, which is the basic requirement to deal with complexity of modern systems. In Network on chip topology design is one of the significant factors that affect the net delay of the system. In this paper mesh topology and torus topology are compared in terms of network delay for a given NOC application using Xillinc 9.1c.]]>
<![CDATA[Optimization of Resource Utilization of Fast Fourier Transform ]]>
<![CDATA[Subhash Chandra Yadav]]>;
<![CDATA[Pradeep Juneja]]>;
<![CDATA[R. G. Varshney]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 6, No 3: November 2017 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v6.i3.pp186-190
<![CDATA[This paper considers the optimization of resource utilization for three FFT algorithms, as it pertains not to the input samples or output modes, but to the twiddle factors that arise in Cooley-Tukey FFT algorithms. Twiddle factors are a set of complex roots of unity, fixed by the transform order for the particular algorithm. This paper shows the comparison between three known FFT algorithms, DIT-FFT, DIF-FFT and GT algorithm. All these algorithms are implemented on FPGA (Spartan-3 XC3S4000l-4fg900) with XILINX 10.1 ISE.]]>
<![CDATA[Design and Development of ARM9 Evaluation Kit for Embedded Applications ]]>
<![CDATA[Nikhil Alex Thomas]]>;
<![CDATA[Sanket Dessai]]>;
<![CDATA[S.G. ShivaPrasad Yadav]]>;
<![CDATA[Shilpa Chaudhari]]>
<![CDATA[ International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 3, No 2: July 2014 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/ijres.v3.i2.pp62-75
<![CDATA[In contrast with low end microprocessor, ARM9 core is quite a sophisticated processor. The Evaluation kit plays an important role in the prototype development and verification of the system design before taking to its actual system development hence it’s provide better confidence to the designer. In this paper a project for the Evaluation kit has been designed for embedded system engineer to implement and confirm the functionality of their operating systems which could lead to a comfortable deployment. The independent modules for the interfaces of the ARM9 processor have been designed and the schematics have been developed using OrCAD. From the tested schematics designed in OrCAD, the related PCB is designed using CADSTAR. An eight-layer board is designed for its signal integrity and complexity of the schematic designed. The designed PCB layer is then calibrated and Gerber files are then made and passed on the PCB board manufacturer for PCB fabrication. The PCB board made is then tested for interconnection continuity using multi-meter as the components are loaded on to the board.]]>
