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International Journal of Reconfigurable and Embedded Systems (IJRES)
Published by Institute of Advanced Engineering and Science
ISSN : 20894864     EISSN : 27222608     DOI : -
Core Subject : Economy,
Economics, Econometrics & Finance
The centre of gravity of the computer industry is now moving from personal computing into embedded computing with the advent of VLSI system level integration and reconfigurable core in system-on-chip (SoC). Reconfigurable and Embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems, ranging from audio-video-equipment, telephones, vehicles, toys, aircraft, medical diagnostics, pacemakers, climate control systems, manufacturing systems, intelligent power systems, security systems, to weapons etc. The aim of IJRES is to provide a vehicle for academics, industrial professionals, educators and policy makers working in the field to contribute and disseminate innovative and important new work on reconfigurable and embedded systems. The scope of the IJRES addresses the state of the art of all aspects of reconfigurable and embedded computing systems with emphasis on algorithms, circuits, systems, models, compilers, architectures, tools, design methodologies, test and applications.
Arjuna Subject : -
Articles 456 Documents
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Energy-efficient routing protocol for wireless sensor networks based on progressive and concentric clusters Adil Hilmani; Mohamed Koundi; Yassine Sabri; Abderrahim Maizate
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 3: November 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i3.pp488-495

Abstract

Smart parking is common in contemporary cities. These smart parking lots are outfitted mostly with wireless sensor networks (WSNs), which are used to detect, monitor, and collect data on the availability status of all existing parking spaces in a given area. Sensors make up WSN, which may gather, process, and transmit informations to the sink. However, the power and communication limitations of the sensors have an effect on the performance and quality of the WSNs. The decrease in the battery and the energy of the nodes causes a decrease in the life of the nodes and also of the entire WSN network. In this article, we present a routing protocol that implements an efficient and robust algorithm allowing the creation of clusters so that the base station can receive data from the entire WSN network. This protocol adopts a reliable and efficient algorithm allowing to minimize the energy dissipation of the sensors and to increase the lifetime of the WSN. In comparison to alternative parking lot management protocols already in use, the simulation results of the proposed protocol are effective and robust in terms of power consumption, data transmission reliability, and WSN network longevity.
Empirical analysis of power side-channel leakage of high-level synthesis designed AES circuits Takumi Mizuno; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 3: November 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i3.pp305-319

Abstract

Many internet of things (IoT) devices and integrated circuit (IC) cards have been compromised by side-channel attacks. Power-analysis attacks, which identify the secret key of a cryptographic circuit by analyzing the power traces, are among the most dangerous side-channel attacks. Gen-erally, there is a trade-off between execution time and circuit area. However, the correlation between security and performance has yet to be determined. In this study, we investigate the cor-relation between side-channel attack resistance and performance (execution time and circuit area) of advanced encryption standard (AES) circuits. Eleven AES circuits with different performances are designed by high-level synthesis and logic synthesis. Of the eleven AES circuits, six are circuits with no side-channel attack countermeasures and five are circuits with masking countermeasures. We employ four metrics based on a T-test to evaluate the side-channel attack resistance. The results based on the correlation coefficient show the correlation between side-channel attack resistance and performance. The correlation varies according to four metrics or masking countermeasure. We argue that designers should change their attitudes towards circuit design when considering security.
Efficient very large-scale integration architecture design of proportionate-type least mean square adaptive filters Lakshmaiah, Gangadharaiah Soralamavu; Narayanappa, Chikkajala Krishnappa; Shrinivasan, Lakshmi; Narasimhaiah, Divya Muddenahalli
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i1.pp69-75

Abstract

The effectiveness of adaptive filters are mainly dependent on the design techniques and the algorithm of adaptation. The most common adaptation technique used is least mean square (LMS) due its computational simplicity. The application depends on the adaptive filter configuration used and are well known for system identification and real time applications. In this work, a modified delayed μ-law proportionate normalized least mean square (DMPNLMS) algorithm has been proposed. It is the improvised version of the µ-law proportionate normalized least mean square (MPNLMS) algorithm. The algorithm is realized using Ladner-Fischer type of parallel prefix logarithmic adder to reduce the silicon area. The simulation and implementation of very large-scale integration (VLSI) architecture are done using MATLAB, Vivado suite and complementary metal–oxide– semiconductor (CMOS) 90 nm technology node using Cadence register transfer level (RTL) Genus Compiler respectively. The DMPNLMS method exhibits a reduction in mean square error, a higher rate of convergence, and more stability. The synthesis results demonstrate that it is area and delay effective, making it practical for applications where a faster operating speed is required.
Timing issues on power side-channel leakage of advanced encryption standard circuits designed by high-level synthesis Miura, Yuto; Nishikawa, Hiroki; Kong, Xiangbo; Tomiyama, Hiroyuki
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 3: November 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i3.pp616-624

Abstract

In recent years, field programmable gate array (FPGA) have been used in many internet of things (IoT) devices and are equipped with cryptographic circuits to ensure security. However, they are exposed to the risk of cryptographic keys being stolen by side-channel attacks. Countermeasures against side-channel attacks have been developed, but they are becoming more of a threat to IoT devices due to the diversity of attacks. Therefore, it is necessary to understand the basic characteristics of side-channel attacks. Therefore, this study clarifies the relationship between two timing issues, the clock period of the circuit and the power sampling interval, and the amount of side-channel leakage. We design seven advanced encryption standard (AES) circuits with different clock periods and conduct empirical experiments using logic simulations to clarify the correlation between the two timings and the amount of side-channel leakage. T-test is used to evaluate the leakage amount, which is evaluated based on four metrics. From the results, we argue that the clock period and sampling interval do not interfere with each other in the side-channel leakage amount.
Design of fault tolerant algorithm for network on chip router using field programmable gate array Shahane, Priti; Kurup, Rakhi
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i1.pp1-8

Abstract

Many internet protocol (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on Field programmable gate array (FPGA).
Hybrid fault tolerant cost aware mechanism for scientific workflow in cloud computing Doddaiah, Chaya T.; Rafi, Mohamed
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i2.pp372-382

Abstract

Cloud computing provides solutions for diverse commercial and academic applications which is the primary goal. Scientific workflows are used in the cloud-computing environment to analyses large-scale scientific applications. For scientific workflows, many data is required, and a single scientific workflow that includes hundreds of stages, depending on the application's time restrictions, task failures, money limits, incorrect task organization, and task management issues can all hinder the implementation of scientific methods. In light of this, a cloud-based scientific workflow management and scheduling system that is fault-tolerant and data-oriented method are proposed. This research designs a novel hybrid cost-aware fault tolerant (HCFT) mechanism for minimizing the cost. Moreover, HCFT integrates optimal clustering and efficient resource utilization through parallel and distributed execution. Novelty of HCFT lies in novel clustering of the similar task for improvisation, CyberShake, laser interferometer gravitational wave observatory (LIGO), Montage, and sRNA identification protocol using high throughput technology (SIPHT) processes are used in the simulations to evaluate the performance of the proposed approach.
Arowana cultivation water quality monitoring and prediction using autoregressive integrated moving average Daru, April Firman; Susanto, Susanto; Adhiwibowo, Whisnumurti
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 3: November 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i3.pp665-673

Abstract

Decorative fish is a fish that humans keep for amusement. There are many decorative fish that exist in this world, one of them is known as the Arowana fish (Scleropages Formosus). This fish is known around Asia including in Indonesia. However, to ensure the Arowana is living well is not easy. The water quality inside a farm must follow a strict balance. The pH of the water must not exceed or below 7 pH. Meanwhile, the total dissolved solid (TDS) salt must not exceed 1000 parts per million. If the balance collapsed, the Arowana fish will not grow. Thus, the owner must monitor the water to make sure that the water is ideal. There were many approaches including internet of things (IoT) solutions. However, they have weaknesses with prediction. Because of this reason, this study designed pH and TDS monitoring with autoregressive integrated moving average (ARIMA) as the algorithm. To achieve the solution, this study used experiment methodology as the research fundamental from top to bottom. According to the evaluation, this study found that the accuracy of ARIMA model is 98.12% for pH and 98.86% for TDS. On the contrary, the seasonal autoregressive integrated moving average (SARIMA) model has an accuracy of 98.52% for pH and 99.89% for TDS.
Low-cost electrocardiogram monitoring system for elderly people using LabVIEW Yauri, Ricardo; Delgado, Max; Flores, Enzo; LLerena, Oscar
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i2.pp483-490

Abstract

Cardiovascular diseases increase due to factors such as obesity, an inadequate diet, and are a problem due to shortages of medical personnel and hospitals. In this case, the implementation of technological solutions is presented as a necessity to prevent heart diseases. Various approaches are used to design low-cost electrocardiogram (ECG) devices, from the use of Bluetooth technology to facilitate data transmission, to the development of wearable ECG devices that use artificial intelligence. The objective is to develop a monitoring system in LabVIEW to visualize the heart rhythms of older adults in the city of Lima (Peru), focusing on ease of use and adaptation to their needs, with the purpose of collaboration between health professionals. A development approach is used that encompasses design, implementation, and iterative testing, as well as practical evaluations and pilot testing. As a result, the correct functioning of the ECG device was validated. Electronic components and electrodes were integrated into the board to capture cardiac signals, energized with batteries and sending the information to an interface in LabVIEW. In conclusion, a portable ECG device has been developed that uses operational amplifiers (Op-amps) and analog filters to reduce noise in cardiac measurements and an intuitive interface in LabVIEW
A novel smart irrigation framework with timing allocation using solenoid valves and Arduino microcontroller Ramakrishnaiah, Vijaya Kumar Hemapura; Lakshmappa, Harish; Gururaj, Bharathi; Muniyappa, Ramesha; Siddaramaiah, Pavan Godekere; Bylamurthy, Nagesh Hunnigere
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 3: November 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i3.pp758-766

Abstract

Irrigation in agriculture is the most common way of providing water to agricultural land or fields at normal stretches through channels and embedded platforms with the internet of things (IoT), to upgrade rural development. In this paper, the arrangement of the various types of irrigation systems and embedded platforms for agriculture was studied. The embedded platform can be designed in a suitable framework that can assist the irrigation system in growing more water-required crops. In this work, three relay switches, two solenoid valves, and one water pump source were connected to Arduino ESP32. The free version of Sinric Google Cloud was utilized significantly to control three devices namely, two solenoid valves using two relay switches and a water pump source using one relay switch. The experiment was executed in a prototype manner with timing allocation by considering two agricultural fields where water was supplied either in one field at a time and showed more prominent results to save time, replacement of manual valves, man intervention, power, and suitable quantity of water for more water-required crops namely, arecanut and coconut.
Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder Daniel, Ravuri; Prasad, Bode; Chaturvedi, Abhay; Balaswamy, Chinthaguntla; Sudarsa, Dorababu; Vinodhkumar, Nallathambi; Eamani, Ramakrishna Reddy; Sudhakar, Ambarapu; Rajanna, Bodapati Venkata
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i1.pp59-68

Abstract

The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.

Page 30 of 46 | Total Record : 456

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