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Buletin Ilmiah Sarjana Teknik Elektro
Published by Universitas Ahmad Dahlan
ISSN : 26857936     EISSN : 26859572     DOI : 10.12928
Core Subject : Engineering,
Electrical & Electronics Engineering
Buletin Ilmiah Sarjana Teknik Elektro (BISTE) adalah jurnal terbuka dan merupakan jurnal nasional yang dikelola oleh Program Studi Teknik Elektro, Fakultas Teknologi Industri, Universitas Ahmad Dahlan. BISTE merupakan Jurnal yang diperuntukkan untuk mahasiswa sarjana Teknik Elektro. Ruang lingkup yang diterima adalah bidang teknik elektro dengan konsentrasi Otomasi Industri meliputi Internet of Things (IoT), PLC, Scada, DCS, Sistem Kendali, Robotika, Kecerdasan Buatan, Pengolahan Sinyal, Pengolahan Citra, Mikrokontroller, Sistem Embedded, Sistem Tenaga Listrik, dan Power Elektronik. Jurnal ini bertujuan untuk menerbitkan penelitian mahasiswa dan berkontribusi dalam pengembangan ilmu pengetahuan dan teknologi.
Arjuna Subject : -
Articles 295 Documents
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Improved DeepFake Image Generation Using StyleGAN2-ADA with Real-Time Personal Image Projection Abed, Ali A.; Talib, Doaa Alaa; Sharkawy, Abdel-Nasser
Buletin Ilmiah Sarjana Teknik Elektro Vol. 7 No. 4 (2025): December
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v7i4.14659

Abstract

This paper presents an improved approach for DeepFake image generation using StyleGAN2-ADA framework. The system is designed to generate high-quality synthetic facial images from a limited dataset of personal photos in real time. By leveraging the Adaptive Discriminator Augmentation (ADA) mechanism, the training process is stabilized without modifying the network architecture, enabling robust image generation even with small-scale datasets. Real-time image capturing and projection techniques are integrated to enhance personalization and identity consistency. The experimental results demonstrate that the proposed method achieve a very high generation performance, significantly outperforming the baseline StyleGAN2 model. The proposed system using StyleGAN2-ADA achieves 99.1% identity similarity, a low Fréchet Inception Distance (FID) of 8.4, and less than 40 ms latency per generated frame. This approach provides a practical solution for dataset augmentation and supports ethical applications in animation, digital avatars, and AI-driven simulations.
Power System Stabilizer Optimization Based on Modified Black‑Winged Kite Algorithm Aribowo, Widi; Abualigah, Laith; Oliva, Diego; B, Nur Vidia Laksmi; Amaliah, Fithrotul Irda; Aziz, As’ad Shidqy; Zangana, Hewa Majeed
Buletin Ilmiah Sarjana Teknik Elektro Vol. 7 No. 4 (2025): December
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v7i4.14669

Abstract

This article presents a Modified Method for tuning the parameters of a power system stabilizer (PSS). This article suggests a different approach that modifies the Black Kite Algorithm (BKA). The Black Kite (BKA) method is inspired by the migratory and predatory habits of the black kite. BKA combines the Leader and Cauchy mutation strategies to improve the algorithm's capacity for global search and convergence rate. This article includes comparative simulations of the PSS objective function and transient response to verify the effectiveness of the suggested strategy. The study validates the proposed method through comparison with both conventional techniques and the original BKA. Simulation results demonstrate that, when benchmarked against competing algorithms, the proposed method consistently yields optimal performance and exhibits faster convergence in certain scenarios. Notably, it reduces undershoot and overshoot by an average of 65% and 90.22%, respectively, compared to the PSS-Lead Lag method. Furthermore, the proposed approach not only minimizes overshoot and undershoot but also achieves a significantly faster settling time.
RoboVR: A Digital Twin Based Framework for Low-Cost 4DoF Robotic Arm Control Wiriasto, Giri Wahyu; Sendari, Siti; Lestari, Dyah; Iqbal, Muhamad Syamsu; Mochtar, Norrima
Buletin Ilmiah Sarjana Teknik Elektro Vol. 7 No. 4 (2025): December
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v7i4.14703

Abstract

The growing need for remote operation in risky situations has encouraged the use of robots that can be controlled from virtual environments. Integrating digital twin and virtual reality offers a way to monitor and control physical systems in three dimensional space. However, many existing implementations still depend on expensive robotic hardware and closed-loop control, while digital twin and virtual reality in open-loop mode is rarely reported and still faces the lack of feedback and the risk of mismatch between virtual motion and physical motion.This study proposes an experimental digital twin and virtual reality framework built on lightweight hardware to control a 4-DoF robotic arm using Arduino and PCA9685, with Unity acting both as the digital twin environment and as the source of kinematic commands. Method covers integration design, calibration of Unity angle to PWM mapping, execution on servos, and preparation of data to compare virtual joint angles with measured servo angles. Testing and validation were carried out through stepwise rotation of the ‘Base’, ‘Shoulder’, ‘Elbow’, and ‘End-effector’ joints to evaluate how well the physical motion followed the virtual model. Results show that the right and left ‘Base’ joints achieved small mean errors of -1.60 and 1.8 degrees, with variance of 1.35 and 1.62. The ‘Elbow-down’ motion was also accurate with a mean error of 1.43 degrees and a variance of 0.98. The largest deviation occurred in the ‘Shoulder’ joint, at -10.67 and 26.5 degrees. These findings confirm that open-loop digital twin and virtual reality control is feasible for low-cost platforms.
Banana Blossom as a Novel Ingredient in The Zero Waste Strategy: Application in Flakes Rahmadhia, Safinta Nurindra; Sari, Meta; Wahyudi, Maulidya Eka; Ibdal; Fitriani, Aprilia; Jebreen, Ali
Buletin Ilmiah Sarjana Teknik Elektro Vol. 7 No. 4 (2025): December
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v7i4.14976

Abstract

Banana bud is an underutilized byproduct of the banana plant. Banana bud is rich in fiber and macronutrients that promote health. The potential of banana bud can be optimized by transforming it into convenient ready-to-eat food products. This study was contributed to facilitate the conversion of agricultural waste into nutrient-dense functional foods. This investigation will involve the preparation of flakes using banana bud flour and arrowroot flour as substitutes for wheat flour. Each mixture incorporated banana bud and arrowroot flour at concentrations of 5%, 10%, and 15%. Additionally, the flakes will undergo assessment of their chemical, physical, and sensory characteristics. The incorporation of banana bud and arrowroot flour into the flakes resulted in a considerable increase in total protein and crude fiber values compared to the control sample. The hardness and crunchiness of the flakes varied considerably, although the water absorption capacity rose markedly. The incorporation of banana bud flour resulted in the flakes acquiring a reddish hue. The outcomes of the descriptive sensory evaluation yielded an assessment of color, odor, texture, flavor, aftertaste, and texture after rehydration conducted by the panellists. The study's results indicate that banana plant waste can be utilized to produce nutrient-dense food products favored by panellists.
Modified Starch-Based Materials for Sustainable Food Packaging Kusuma, Isnainul; Rahmadhia, Safinta Nurindra; Ma'arif, Alfian; Aktawan, Agus; Juwitaningtyas, Titisari; Ramli, Nor Hanuni; Olunusi, Samuel Olugbenga
Buletin Ilmiah Sarjana Teknik Elektro Vol. 8 No. 1 (2026): February
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v8i1.15092

Abstract

Food packaging is a significant contributor to plastic waste, prompting a search for sustainable alternatives. Among these alternatives, modified starch-based materials have emerged as promising solutions due to their biodegradability, renewability, and abundance. However, the hydrophilic nature, poor mechanical properties, and limited thermal stability of native starch pose challenges for its use in food packaging. This review explores various modification techniques—chemical, physical, and enzymatic—that enhance the performance of starch-based materials for food packaging. The methods discussed include acetylation, crosslinking, heat-moisture treatments, and enzymatic hydrolysis, each improving the material's strength, flexibility, and barrier properties. Results demonstrate that starch modifications significantly improve the mechanical, thermal, and water vapor barrier properties of packaging films. Notably, the combination of modified starch with other biopolymers such as chitosan or gelatin further enhances these properties, making them suitable for active packaging applications. The incorporation of antimicrobial agents and nanofillers into starch-based films has expanded their functionality, enabling food shelf-life extension and quality monitoring. Despite these advancements, challenges remain in balancing the biodegradability and durability of starch-based films. Future research should focus on optimizing modification processes, enhancing scalability, and addressing regulatory concerns to ensure the commercial viability of modified starch as an eco-friendly packaging material.
A Novel Approach to Energy Efficient Wireless Communication in Internet of Things Networks Alfaisaly , Noor Nateq; Saeed, Elaf A.; Younis, Saad B.; Naeem, Suhad Qasim
Buletin Ilmiah Sarjana Teknik Elektro Vol. 8 No. 1 (2026): February
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v8i1.13868

Abstract

One of the key issues of Internet of Things (IoT)-based wireless sensor networks (WSNs) is energy efficiency because battery-powered nodes have to work within a set of severe resource limitations. Conventional protocols do not always work well in nonhomogeneous dynamic environments and this results in poor performance and longevity. The design and validation of an unified framework that intelligently operates network clustering, routing, and resource allocation with the use of machine learning are the research contributions. The framework is represented through a dynamic clustering scheme based on neural networks, routing scheme based on reinforcement learning (Q-learning) and a scheme of Lagrangian optimization-based resource allocation. MATLAB and NS-3 simulations were run with different sizes of networks (100-500 nodes) and traffic. The flow of methodology has formed a scheme whereby the adaptive decision-making was to be made at several levels of the communication stack. The average power savings, increment in network lifetime, and improvement in the percentage packet delivery ratio of the proposed model was 31, 17.9 and 6.2, respectively, over the classical schemes like LEACH and TEEN. Findings were also uniform at various levels of deployments and statistical validation was made to prove it is significant (p < 0.01). The model exhibits better adaptability and performance aspects in both the case of a static network and dynamic network as compared to the recent machine learning-based approaches. To sum up, the paper provides a scaled, smart communication system of IoT networks. Its applications in a real world can be found in smart farming, industrial IoT, and healthcare. The next steps involve the prototype development and integration of the blockchain based node authentication.
Design and Development of ALU using Multi Chiplet Methodology for High-Performance Computing Rai, Amrita; Shah, Owais Ahmad; Khan, Imran Ahmed; Khan, Mubeen Ahmad; Jindal, Latika; Chouhan, Piyush
Buletin Ilmiah Sarjana Teknik Elektro Vol. 8 No. 1 (2026): February
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v8i1.14107

Abstract

The fundamental programmable logic unit (PLU) in any microprocessors or a microcontrollers and real-time processor of integrated circuits is the arithmetic and logical unit (ALU). The conventional ALUs had exorbitant power consumptions, route delays, and transistor counts because they were created using complementary metal oxide semiconductor (CMOS) technology. Therefore, the motivation of this paper is on the design and development of ALU using Multi Chiplet design Methodology with FPGA kit and simulation is perform on vivado software. Multi-Chiplet systems helps reduce the cost of chip design, low power consumption and increases yield for complicated SoCs (System on Chips). Low power with less design space semiconductors will be the future of computing as the power requirements and size of the SoC cannot be expanded above the set limit. There is a need to reconsider how the design ALU to shorten the time needed for their development as designer continue to push the current limit boundaries of the present CMOS process. This paper proposed a Multi Chiplet SoC structure of ALU with low power, less area required and in small packaging for mostly used in CPU of all type computing devices. The basic function of ALU is to perform arithmetic and Logic operations, required multiplication and additions. In this paper booth multiplier and Kogee-Stone Adder are proposed with multi-chip module (MCM) for low power consumption, less area requirement, high processing speed and less delay. Due to the ever-growing requirements of increasing the Floating-Point Operations per Second (FLOPs) of the processing unit in the field of high-performance computing and AI, there needs to be changes in both the overall design and also the design methodology in fabricating an ALU.
Implementation of an Automatic Controlled Power Factor Correction System Utilizing Low-Cost Modules Sneineh , Anees Abu; Salah, Wael A.; Ma'arif, Alfian
Buletin Ilmiah Sarjana Teknik Elektro Vol. 8 No. 1 (2026): February
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v8i1.14215

Abstract

This paper presents the design and implementation of a PIC microcontroller-based power factor correction system using a stepped capacitor bank and low-cost analog measurement modules. The proposed design aimed to address the low power factor issue caused by inductive loads that intern increases the current, losses, and apparent power demand. The developed PIC-based controller integrated analog conditioning circuits for voltage, current, and phase-angle measurement. The proposed system acquires analog signals from a voltage transformer, a current transformer–op-amp module, and an AD8302-based phase detector, computes real, reactive, and apparent power in real time, and automatically connects or disconnects capacitor-bank steps to maintain the power factor within a predefined band (0.92–0.98). Experimental results on a 4 kW inductive load array indicated that the measurement error of the analog voltage module was approximately 1.32%, while the analog current module exhibited an error of around 3.02% in comparison to digital measuring instruments. Additionally, there was an improvement in the power factor from 0.865 to 0.935, with by a reduction in load current of approximately 7% and a decrease in load reactive power of about 35%. The proposed design confirms satisfactory operation for automatic capacitor-bank control in power factor correction applications.
Optimization of DC Fast Charging in CHAdeMO Systems Using Thunderstorm Algorithm with Thermal and Health Constraints Samsurizal, Samsurizal; Afandi, Arif Nur; Faiz, Mohamad Rodhi
Buletin Ilmiah Sarjana Teknik Elektro Vol. 8 No. 1 (2026): February
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v8i1.14505

Abstract

The significant increase in the use of electric vehicles (EVs) demands the development of fast charging systems that are not only efficient but also maintain battery integrity. One of the primary challenges in direct current (DC) charging is balancing speed with minimizing degradation caused by thermal stress. This study proposes a charging optimization model based on the Thunderstorm Optimization Algorithm (TA) for CHAdeMO-based DC systems. A lithium-ion equivalent circuit battery model was used to simulate electrochemical and thermal dynamics. The model introduces an adaptive charging current profile designed with a dynamic boundary configuration, defined here as the iterative adjustment of current limits according to real-time thermal and health constraints. Compared to conventional constant current–constant voltage (CC–CV) methods, TA considers maximum temperature, State of Health (SoH), and target State of Charge (SoC) simultaneously. The simulation (180 minutes, passive cooling, Python-based) showed that TA reduced SoH degradation to 1.3% and battery life usage to 18.4%—the latter defined as cumulative stress energy normalized to initial capacity—compared to 2.9% and 22.5% for CC–CV. Additionally, TA achieved a higher average charging power (26.1 kW vs. 24.8 kW) without exceeding 50 °C. Although the algorithm requires more computational effort than CC–CV, its moderate complexity suggests feasibility for real-time integration in battery management systems. These findings highlight TA as a promising adaptive and sustainability-oriented charging strategy.
Investigation of Manufacture Tolerances on Torque Pulsation Profile of Interior Permanent Magnet Motor with Third Harmonic Injected Sinusoidal Rotor Iron Pole Shuraiji, Ahlam Luaibi; Hameed, Kassim Rasheed; Shneen, Salam Waley
Buletin Ilmiah Sarjana Teknik Elektro Vol. 8 No. 1 (2026): February
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/biste.v8i1.14647

Abstract

Torque ripple is a significant undesirable aspect of permanent magnet (PM) machine. It is mainly contributed by cogging torque, which is inherit feature of the PM machine. Interior permanent magnet (IPM) motor with a sinusoidal + third-order harmonic injected rotor pole shape has been introduced as one of the most efficient rotor pole arc iron shape techniques to minimize the cogging torque. Such method showed a reduction in the cogging torque compared to the traditional designs. Generally, imperfections in the manufacturing process can exacerbate cogging torque and, by extension, torque ripple. This research assesses how manufacturing tolerances influence the torque ripple of the IPM motor having sinusoidal + third order harmonic rotor pole shape. The investigation has been carried out using two-dimension finite element analysis(2D-FEA) method, ANSOFT MAXWELL program. Different models of the IPMs with sinusoidal + third order harmonic rotor pole shape have been made to simulate healthy, eccentricity and PM diversity cases. According to the simulation results, it has been found that PM diversity leads to introduce additional harmonics in the cogging torque waveforms, i.e., in addition to the fundamental harmonic, which is the 60th harmonic orders, the 12th harmonic and its multiples harmonic orders were presented, consequently resulting in increasing the torque ripple. Moreover, the obtained results have shown that the static eccentricity has more negative effect on the torque ripple compared to the dynamic counterpart, i.e. the torque ripple of the static eccentricity is about 20% higher than that of the dynamic counterpart.

Page 29 of 30 | Total Record : 295

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