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Journal : Eduvest - Journal of Universal Studies

Application of Exponential Smoothing Method for Forecasting Spare Parts Inventory at Heavy Equipment Distributor Company Budiarto, Despiyan Dwi; Miftahudin, Miftahudin; Riwurohi, Jan Everhard
Eduvest - Journal of Universal Studies Vol. 4 No. 3 (2024): Journal Eduvest - Journal of Universal Studies
Publisher : Green Publisher Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.59188/eduvest.v4i3.1079

Abstract

PT. Kobexindo Tractors Tbk holds a significant spare parts inventory to meet their customers' needs. Over the period from 2016 to 2023, the company experienced an average annual loss of Rp. 1,176,438,113, due to the inadequate analysis of spare parts demand, which serves as a reference in the procurement process. To address this issue, this research focuses on developing a model that can generate accurate forecasts for spare parts inventory, particularly Jungheinrich parts, to support appropriate management decisions in the procurement process at the company. The Exponential Smoothing method is chosen for its ability to handle data with fluctuating patterns and trends. This study will compare the Simple Exponential Smoothing, Double Exponential Smoothing, and Triple Exponential Smoothing methods. The data ratio used in this research is 70% for training data and 30% for testing data. The prototype development is conducted using the Python programming language. The research results indicate that the Holts Winter Exponential Smoothing Model with Multiplicative Seasonality and Multiplicative Trend (Triple Exponential) is the best method among others, as follows: 1) Train RSME (7.082307), a low RSME value on training data indicates that this model has a small prediction error rate on the data used for training. 2) Test MAPE (6.343268), a low MAPE value on test data indicates that this model provides fairly accurate predictions in percentage terms of the actual values. 3) Test RSME Values (23.160521), a sufficiently low RSME value on test data indicates that this model also successfully generalizes well on unseen data.
The Role of Cache Memory In Enhancing Microprocessor Performance in PT. Srikandi Sinergi Sakti Hendarin, Hendarin; Riwurohi, Jan Everhard; Arachman, Setyo Arief
Eduvest - Journal of Universal Studies Vol. 4 No. 12 (2024): Journal Eduvest - Journal of Universal Studies
Publisher : Green Publisher Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.59188/eduvest.v4i12.43139

Abstract

Cache memory in microprocessors has an important role in improving computer system performance by reducing data access time. This research aims to test the hypothesis that increasing the size and level of cache memory can significantly improve microprocessor performance. The research methodology involves a literature study on the concept of cache memory and experimental simulations using computer architecture simulators, such as Gem5, to model scenarios with varying cache sizes and levels. In these simulations, performance parameters such as memory access latency, throughput, and Instructions Per Cycle (IPC) were measured and analyzed. The results show that increasing cache size and level generally contributes towards improving microprocessor performance by reducing data access time. Further statistical analysis supports the hypothesis that there is a positive correlation between cache size and level and system efficiency. These findings provide useful insights in future microprocessor architecture design and memory system optimization.
Smart Strategies in Hardware Provisioning for Ai Solutions in The Cloud Hambali, Yusuf; Riwurohi, Jan Everhard; Akbar, Victor
Eduvest - Journal of Universal Studies Vol. 4 No. 12 (2024): Journal Eduvest - Journal of Universal Studies
Publisher : Green Publisher Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.59188/eduvest.v4i12.43140

Abstract

Rapid developments in artificial intelligence (AI) have driven the need for more efficient and powerful computing infrastructure, especially in cloud environments. This research explores smart strategies in providing hardware for AI solutions in the cloud, focusing on the latest innovations in AI hardware such as neuromorphic chips, FPGAs, and ASICs. Through a comprehensive analysis of the current literature, performance benchmarks, and implementation case studies, the study identifies several key strategies. Key findings include the effectiveness of hybrid architectures that combine different types of AI hardware, the potential for resource disaggregators and composable architectures to improve flexibility and efficiency, and the importance of specific acceleration for different phases in the AI pipeline. The study also emphasizes the significance of performance optimization and energy efficiency, as well as the integration of security and data privacy features in AI hardware design. Challenges such as standardization, scalability, and complexity management are discussed along with future opportunities in green AI and computing-in-memory. In conclusion, implementing a smart strategy in the provision of AI hardware in the cloud requires a holistic approach that considers workload diversity, architectural flexibility, energy efficiency, and security aspects. This research provides valuable insights for cloud service providers, hardware manufacturers, and AI practitioners in optimizing infrastructure to support AI innovation in the cloud computing era.
Next-Generation CPU Architectures: A Study of the Influence of Nanometer Technology on Computer Performance Sudija, Ija; riwurohi, Jan everhard; Masad, Muhamad Masruin
Eduvest - Journal of Universal Studies Vol. 4 No. 12 (2024): Journal Eduvest - Journal of Universal Studies
Publisher : Green Publisher Indonesia

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.59188/eduvest.v4i12.44711

Abstract

Nanometer technology has become one of the most significant innovations in the advancement of modern CPU architecture, enabling substantial improvements in computational performance, energy efficiency, and transistor density. This study examines the impact of 7nm, 5nm, and 3nm technology implementation on CPU performance under various workload scenarios, including multitasking, graphics rendering, and artificial intelligence-based applications. Based on a series of experimental tests, the findings indicate that reducing transistor size directly increases processor speed by up to 30% while reducing power consumption by 20%. However, challenges such as heat dissipation and power leakage become more pronounced with technology below 5nm. Several proposed solutions include the development of more advanced cooling systems and the use of alternative semiconductor materials, such as graphene, to mitigate power leakage. This research provides valuable insights into the future development of CPU architecture and its impact on the technology industry as a whole.