Articles
<![CDATA[Noise and Bandwidth Consideration in Designing Op-Amp Based Transimpedance Amplifier for VLC ]]>
<![CDATA[Trio Adiono]]>;
<![CDATA[Rachmad Vidya Wicaksana Putra]]>;
<![CDATA[Syifaul Fuada]]>
<![CDATA[ Bulletin of Electrical Engineering and Informatics Vol 7, No 2: June 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/eei.v7i2.870
<![CDATA[In a visible light communication (VLC) system, there are many modules involved. One of the important modules is Transimpedance Amplifier (TIA) that resides in the analog front-end receiver (Rx-AFE). TIA is responsible for performing signal conversion from current signal, which is provided from the photodiode (PD) to voltage signal. It is the reason why the TIA should be operating in low noise condition and wide bandwidth of frequency. These will enable a flexible coverage of the VLC system in performing its signal processing. Hence, in this research, we provide considerations of the noise and frequency bandwidth analysis in designing TIA to cope with the required design specification of a VLC system.]]>
<![CDATA[Curtain Control Systems Development on Mesh Wireless Network of the Smart Home ]]>
<![CDATA[Trio Adiono]]>;
<![CDATA[Sinantya Feranti Anindya]]>;
<![CDATA[Syifaul Fuada]]>;
<![CDATA[Maulana Yusuf Fathany]]>
<![CDATA[ Bulletin of Electrical Engineering and Informatics Vol 7, No 4: December 2018 ]]>
Publisher : <![CDATA[Institute of Advanced Engineering and Science ]]>
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DOI: 10.11591/eei.v7i4.1199
<![CDATA[In this paper, a curtain controller for smart home is presented. The aim of this work is to develop an end device in smart home system that will support power conservation function indirectly, specifically a curtain open/close controller. To achieve this, the 28BYJ-48 stepper motor is used as actuator with the assistance of ULN2003A driver. The motor is controlled using STM32L100RCT6 microcontroller, which is chosen due to its low power consumption. The microcontroller controls the motor’s direction by using a pulse width modulation logic signals emitted from four GPIO pins, which works based on data transmitted from central host through ZigBee protocol on Mesh network. Meanwhile, from the user’s side, the control is done by using Android-based application, which is connected to central host through Bluetooth. Based on the testing conducted on a miniature curtain, the curtain can be controlled wirelessly through the Android application. Furthermore, the device consumes power 210.5 mW for idle condition and 1,586 mW for process condition. The amount of the consumed power makes it suitable for low-power operation and in alignment with the smart home system’s overall aim for power conservation in the wireless sensor network-based smart home system.]]>
<![CDATA[A Real-Time Visible Light Communication System on Chip Design for High Speed Wireless Communication ]]>
<![CDATA[Trio Adiono]]>
<![CDATA[ Proceeding of the Electrical Engineering Computer Science and Informatics Vol 6: EECSI 2019 ]]>
Publisher : <![CDATA[IAES Indonesia Section ]]>
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DOI: 10.11591/eecsi.v6.2010
<![CDATA[The increasing demand of wireless communication bandwidth due to advancement of IoT and smartphone technology, requires the new wireless communication technology that can provide high speed wireless communication. The Visible Light Communication (VLC) has been proven can provide multi gigabit wireless communication throughput using unlicensed visible light spectrum. Therefore, VLC is a promising technology to solve bandwidth limitation problem. In order to achieve high speed throughput, VLC signal processing has to be implemented using Application Specific Integrated Circuits (ASICs) technology. In this research, we develop a baseband processor architecture for VLC application. We use System on Chip (SoC) design approach to reduce design time and easy system integration to various applications. In order to increase spectrum efficiency, we utilize OFDM modulation scheme. Several OFDM processing blocks, such as synchronizer, FFT/IFFT, modulator, demodulator, are designed in the system. The real-time system performance is verified in FPGA based system prototyping. The design includes optical wireless front end module, baseband processing and network layer. The developed prototype shows a real-time performance for high speed internet access.]]>
<![CDATA[Smart Navigation Equipment Monitoring System ]]>
<![CDATA[Muhammad Arif Sulaiman]]>;
<![CDATA[Trio Adiono]]>
<![CDATA[ Proceeding of the Electrical Engineering Computer Science and Informatics Vol 7, No 1: EECSI 2020 ]]>
Publisher : <![CDATA[IAES Indonesia Section ]]>
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DOI: 10.11591/eecsi.v7.2061
<![CDATA[Digital image processing is a processing of digital frames using digital computation. Image processing has been used in many sectors such as military, biomedics, and in this paper, the authors will implement it in the civil aviation sector by introducing a new method to monitor an aviation navigation equipment. It can be used on all LED-based Built-in Monitor navigation equipment, despite it is a low-cost system. The image processing of this research is done by doing perspective correction and then continue with BLOB detection in a segmentation stage. The final result will be displayed on a web page. Compared to its predecessor, this method gives better flexibility which does not need to be electrically connected with monitored equipment and not limited to certain brands.]]>
<![CDATA[An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification ]]>
<![CDATA[Trio Adiono]]>;
<![CDATA[Hans G. Kerkhoff]]>;
<![CDATA[Hiroaki Kunieda]]>
<![CDATA[ Journal of ICT Research and Applications Vol. 3 No. 1 (2009) ]]>
Publisher : <![CDATA[LPPM ITB ]]>
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DOI: 10.5614/itbj.ict.2009.3.1.4
<![CDATA[This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which enables core verification at actual speed. It significantly decreases the verification time due to the large number of required test vectors in typical MPEG4 verification. Furthermore, it also makes the system scalable for functional core expansion due to upgrading of standards. The proposed infrastructural IP is also linked to PC-based interactive tools to simplify the verification of individual and integrated cores. It also provides detailed diagnostic data that enables simple system debugging. The debugging tools also feature test-pattern generation and simulation of expected values. Actual system implementation has shown full functionality of our proposed method.]]>
<![CDATA[A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm ]]>
<![CDATA[Rachmad Vidya Wicaksana Putra]]>;
<![CDATA[Rella Mareta]]>;
<![CDATA[Nurfitri Anbarsanti]]>;
<![CDATA[Trio Adiono]]>
<![CDATA[ Journal of ICT Research and Applications Vol. 6 No. 2 (2012) ]]>
Publisher : <![CDATA[LPPM ITB ]]>
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DOI: 10.5614/itbj.ict.2012.6.2.3
<![CDATA[In the literature, several approaches of designing a DCT/IDCT-based image compression system have been proposed. In this paper, we present a new RTL design approach with as main focus developing a DCT/IDCT-based image compression architecture using a self-created algorithm. This algorithm can efficiently minimize the amount of shifter -adders to substitute multiplier s. We call this new algorithm the multiplication from Common Binary Expression (mCBE) Algorithm. Besides this algorithm, we propose alternative quantization numbers, which can be implemented simply as shifters in digital hardware. Mostly, these numbers can retain a good compressed-image quality compared to JPEG recommendations. These ideas lead to our design being small in circuit area, multiplierless, and low in complexity. The proposed 8-point 1D-DCT design has only six stages, while the 8-point 1D-IDCT design has only seven stages (one stage being defined as equal to the delay of one shifter or 2-input adder). By using the pipelining method, we can achieve a high-speed architecture with latency as a trade-off consideration. The design has been synthesized and can reach a speed of up to 1.41ns critical path delay (709.22MHz). ]]>
<![CDATA[VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm ]]>
<![CDATA[Rachmad Vidya Wicaksana Putra]]>;
<![CDATA[Trio Adiono]]>
<![CDATA[ Journal of ICT Research and Applications Vol. 10 No. 1 (2016) ]]>
Publisher : <![CDATA[LPPM ITB ]]>
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DOI: 10.5614/itbj.ict.res.appl.2016.10.1.5
<![CDATA[Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.]]>
<![CDATA[An Inter-Processor Communication (IPC) Data Sharing Architecture in Heterogeneous MPSoC for OFDMA ]]>
<![CDATA[Trio Adiono]]>;
<![CDATA[Rian Ferdian]]>;
<![CDATA[Febri Dawani]]>;
<![CDATA[Imran Abdurrahman]]>;
<![CDATA[Rachmad Vidya Wicaksana Putra]]>;
<![CDATA[Nur Ahmadi]]>
<![CDATA[ Journal of ICT Research and Applications Vol. 12 No. 1 (2018) ]]>
Publisher : <![CDATA[LPPM ITB ]]>
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DOI: 10.5614/itbj.ict.res.appl.2018.12.1.5
<![CDATA[Multiprocessor system-on-chip (MPSoC) promises better data management for parallel processing than conventional SoC. This feature is very suitable for wireless communication systems. Better data processing management can reduce resource utilization and can potentially reduce power consumption as well. Hence, this research aimed to minimize the orthogonal frequency-division multiple access (OFDMA) processing hardware by proposing a new data sharing architecture on a heterogeneous MPSoC platform that incorporates inter-processor communication (IPC), multi-processor, multi-bus, multi-frequency and parallel processing design of the medium access controller (MAC) layer. This MPSoC was designed based on a RISC processor with an AMBA multi-bus system. To achieve high throughput, the proposed MPSoC runs at two different frequencies, 40 MHz and 80 MHz. The proposed system was implemented and verified using FPGA. The verification results showed that the proposed system can work in real-time with a maximum throughput of 11 MBps using a 40 MHz system clock. The proposed MPSoC is a promising solution to perform OFDMA processing on 4G and 5G technologies.]]>
<![CDATA[Desain dan Realisasi Sistem Komunikasi Cahaya Tampak untuk Streaming Teks berbasis PWM ]]>
<![CDATA[Trio Adiono]]>;
<![CDATA[Syifaul Fuada]]>;
<![CDATA[Angga Pradana]]>
<![CDATA[ Setrum : Sistem Kendali-Tenaga-elektronika-telekomunikasi-komputer Vol 6, No 2 (2017): Edisi Desember 2017 ]]>
Publisher : <![CDATA[Fakultas Teknik Elektro - Universitas Sultan Ageng Tirtayasa ]]>
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DOI: 10.36055/setrum.v6i2.2620
<![CDATA[The design and implementation of visible light communication systems for transmitting digital data (texts) have been discussed in this paper. Then, two evaluations were performed also, i.e. the demonstration of streaming text through the visible light as a proof-of-concept system design. The next evaluation is a BER measurement intended to know the VLC system performance quantitatively. The value of BER against the several parameters: by the variation of distance and its reception angle. The proposed VLC system works well until the photodiode reception angle to the LEDs up to 50°. According to evaluation, our system can operate optimally within 30 – 80 cm or 50 – 130 cm of optical channel range depending on the Gain setting option. To support the reliability of noise from ambient light and interference lamps such as fluorescent lamps, the filters circuit are employed: high pass filter and DC-offset remover. Based on the BER analysis, the filters can compensate the problem of ambient light noise (DC-offset signal) and interference lamp (100-150 Hz of carrier frequency). The speed of data-rate obtained with 1-PWM modulation and the low-cost analog component is 3.3 kbps.]]>
<![CDATA[Implementing Smart Mobile Application to Achieve a Sustainable Campus ]]>
<![CDATA[Zainal Rasyid Mahayuddin]]>;
<![CDATA[Nur Afyfah Suwadi]]>;
<![CDATA[Ruzzakiah Jenal]]>;
<![CDATA[Haslina Arshad]]>;
<![CDATA[Trio Adiono]]>
<![CDATA[ International Journal of Supply Chain Management Vol 7, No 3 (2018): International Journal of Supply Chain Management (IJSCM) ]]>
Publisher : <![CDATA[International Journal of Supply Chain Management ]]>
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<![CDATA[The use of technology nowadays is not an unusual matter especially in universities. The use of computer technology and the advanced networking that creates an integrated services and enables communication among the community of universities is a concept in a digital campus. However, in the education sector, the digital campus needs to be built as an essential foundation for the modernization of education and to facilitate a better campus life. This paper presents the concept and framework of Digital Campus as part of the universitys challenges in fostering an economical and socially sustainable campus. The implementation of co-created value in framework increases the efficiency of the digital campus concept. The use of mobile applications is very appropriate for achieving campus sustainability because of its increasing significant and ability. UKM Mobile Application as part of Digital Campus strategy is seen to be able to contribute to the sustainability of the campus. We also present the implementation of Digital Campus based on smart card usage in the applications such as attendance system, canteen payment and academic services. Mobile application development embedding value co-creation can improve the quality of service in terms of good communication with customers and the best services to the university.]]>
